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review.coreboot.org / coreboot / a50ced2eba20a007fa5b486c251c252ad09868cf / . / src / mainboard / thomson / ip1000 / gpio.c
blob: b4bf30e1ed090fb86af0ae45a37a5ad5a2bc7aa5 [file] [log] [blame]
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]15 */
16
Stefan Reinauer63db6142016-02-24 13:25:42 -0800[diff] [blame]17#include <delay.h>
18
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]19#define PME_DEV PNP_DEV(0x2e, 0x0a)
20#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
21#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
22
23/* Early mainboard specific GPIO setup. */
24static void mb_gpio_init(void)
25{
Antonello Dettori12326662016-11-08 18:44:46 +0100[diff] [blame]26 pci_devfn_t dev;
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]27 uint16_t port;
28 uint32_t set_gpio;
29
30 /* Southbridge GPIOs. */
31 /* Set the LPC device statically. */
32 dev = PCI_DEV(0x0, 0x1f, 0x0);
33
34 /* Set the value for GPIO base address register and enable GPIO. */
Stefan Reinauer138be832010-02-27 01:50:21 +0000[diff] [blame]35 pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
36 pci_write_config8(dev, GPIO_CNTL, 0x10);
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]37
38 /* Set GPIO23 to high, this enables the LAN controller. */
39 udelay(10);
40 set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
41 set_gpio |= 1 << 23;
42 outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
43
Joseph Smith06025df2009-05-08 00:19:13 +0000[diff] [blame]44 /* Disable AC97 Modem */
45 pci_write_config8(dev, 0xf2, 0x40);
46
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]47 /* Super I/O GPIOs. */
48 dev = PME_DEV;
49 port = dev >> 8;
50
51 /* Enter the configuration state. */
52 outb(0x55, port);
53 pnp_set_logical_device(dev);
54 pnp_set_enable(dev, 0);
55 pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
56 pnp_set_enable(dev, 1);
57
58 /* GP21 - LED_RED */
59 outl(0x01, PME_IO_BASE_ADDR + 0x2c);
60
61 /* GP30 - FAN2_TACH */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]62 outl(0x05, PME_IO_BASE_ADDR + 0x33);
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]63
64 /* GP31 - FAN1_TACH */
65 outl(0x05, PME_IO_BASE_ADDR + 0x34);
66
67 /* GP32 - FAN2_CTRL */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]68 outl(0x04, PME_IO_BASE_ADDR + 0x35);
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]69
70 /* GP33 - FAN1_CTRL */
71 outl(0x04, PME_IO_BASE_ADDR + 0x36);
72
73 /* GP34 - AUD_MUTE_OUT_R */
74 outl(0x00, PME_IO_BASE_ADDR + 0x37);
75
76 /* GP36 - KBRST */
77 outl(0x00, PME_IO_BASE_ADDR + 0x39);
78
79 /* GP37 - A20GATE */
80 outl(0x00, PME_IO_BASE_ADDR + 0x3a);
81
82 /* GP42 - GPIO_PME_OUT */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]83 outl(0x00, PME_IO_BASE_ADDR + 0x3d);
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]84
85 /* GP50 - SER2_RI */
86 outl(0x05, PME_IO_BASE_ADDR + 0x3f);
87
88 /* GP51 - SER2_DCD */
89 outl(0x05, PME_IO_BASE_ADDR + 0x40);
90
91 /* GP52 - SER2_RX */
92 outl(0x05, PME_IO_BASE_ADDR + 0x41);
93
94 /* GP53 - SER2_TX */
95 outl(0x04, PME_IO_BASE_ADDR + 0x42);
96
97 /* GP55 - SER2_RTS */
98 outl(0x04, PME_IO_BASE_ADDR + 0x44);
99
100 /* GP56 - SER2_CTS */
101 outl(0x05, PME_IO_BASE_ADDR + 0x45);
102
103 /* GP57 - SER2_DTR */
104 outl(0x04, PME_IO_BASE_ADDR + 0x46);
105
106 /* GP60 - LED_GREEN */
107 outl(0x01, PME_IO_BASE_ADDR + 0x47);
108
109 /* GP61 - LED_YELLOW */
110 outl(0x01, PME_IO_BASE_ADDR + 0x48);
111
112 /* GP3 */
113 outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
114
115 /* GP4 */
116 outl(0x04, PME_IO_BASE_ADDR + 0x4e);
117
118 /* FAN1 */
119 outl(0x01, PME_IO_BASE_ADDR + 0x56);
120
121 /* FAN2 */
122 outl(0x01, PME_IO_BASE_ADDR + 0x57);
123
124 /* Fan Control */
125 outl(0x50, PME_IO_BASE_ADDR + 0x58);
126
127 /* Fan1 Tachometer */
128 outl(0xff, PME_IO_BASE_ADDR + 0x59);
129
130 /* Fan2 Tachometer */
131 outl(0xff, PME_IO_BASE_ADDR + 0x5a);
132
133 /* LED1 */
134 outl(0x00, PME_IO_BASE_ADDR + 0x5d);
135
136 /* LED2 */
137 outl(0x00, PME_IO_BASE_ADDR + 0x5e);
138
139 /* Keyboard Scan Code */
140 outl(0x00, PME_IO_BASE_ADDR + 0x5f);
141
142 /* Exit the configuration state. */
143 outb(0xaa, port);
144}