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review.coreboot.org / coreboot / 138be8315b63b0c8955159580d085e7621882b95 / . / src / mainboard / thomson / ip1000 / gpio.c
blob: 6a69bb539d06aefd6e9254b468fbcd38692afc79 [file] [log] [blame]
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#define PME_DEV PNP_DEV(0x2e, 0x0a)
22#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
23#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
24
25/* Early mainboard specific GPIO setup. */
26static void mb_gpio_init(void)
27{
28 device_t dev;
29 uint16_t port;
30 uint32_t set_gpio;
31
32 /* Southbridge GPIOs. */
33 /* Set the LPC device statically. */
34 dev = PCI_DEV(0x0, 0x1f, 0x0);
35
36 /* Set the value for GPIO base address register and enable GPIO. */
Stefan Reinauer138be832010-02-27 01:50:21 +0000[diff] [blame^]37 pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
38 pci_write_config8(dev, GPIO_CNTL, 0x10);
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]39
40 /* Set GPIO23 to high, this enables the LAN controller. */
41 udelay(10);
42 set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
43 set_gpio |= 1 << 23;
44 outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
45
Joseph Smith06025df2009-05-08 00:19:13 +0000[diff] [blame]46 /* Disable AC97 Modem */
47 pci_write_config8(dev, 0xf2, 0x40);
48
Stefan Reinauer88e71e82009-05-02 12:42:30 +0000[diff] [blame]49 /* Super I/O GPIOs. */
50 dev = PME_DEV;
51 port = dev >> 8;
52
53 /* Enter the configuration state. */
54 outb(0x55, port);
55 pnp_set_logical_device(dev);
56 pnp_set_enable(dev, 0);
57 pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
58 pnp_set_enable(dev, 1);
59
60 /* GP21 - LED_RED */
61 outl(0x01, PME_IO_BASE_ADDR + 0x2c);
62
63 /* GP30 - FAN2_TACH */
64 outl(0x05, PME_IO_BASE_ADDR + 0x33);
65
66 /* GP31 - FAN1_TACH */
67 outl(0x05, PME_IO_BASE_ADDR + 0x34);
68
69 /* GP32 - FAN2_CTRL */
70 outl(0x04, PME_IO_BASE_ADDR + 0x35);
71
72 /* GP33 - FAN1_CTRL */
73 outl(0x04, PME_IO_BASE_ADDR + 0x36);
74
75 /* GP34 - AUD_MUTE_OUT_R */
76 outl(0x00, PME_IO_BASE_ADDR + 0x37);
77
78 /* GP36 - KBRST */
79 outl(0x00, PME_IO_BASE_ADDR + 0x39);
80
81 /* GP37 - A20GATE */
82 outl(0x00, PME_IO_BASE_ADDR + 0x3a);
83
84 /* GP42 - GPIO_PME_OUT */
85 outl(0x00, PME_IO_BASE_ADDR + 0x3d);
86
87 /* GP50 - SER2_RI */
88 outl(0x05, PME_IO_BASE_ADDR + 0x3f);
89
90 /* GP51 - SER2_DCD */
91 outl(0x05, PME_IO_BASE_ADDR + 0x40);
92
93 /* GP52 - SER2_RX */
94 outl(0x05, PME_IO_BASE_ADDR + 0x41);
95
96 /* GP53 - SER2_TX */
97 outl(0x04, PME_IO_BASE_ADDR + 0x42);
98
99 /* GP55 - SER2_RTS */
100 outl(0x04, PME_IO_BASE_ADDR + 0x44);
101
102 /* GP56 - SER2_CTS */
103 outl(0x05, PME_IO_BASE_ADDR + 0x45);
104
105 /* GP57 - SER2_DTR */
106 outl(0x04, PME_IO_BASE_ADDR + 0x46);
107
108 /* GP60 - LED_GREEN */
109 outl(0x01, PME_IO_BASE_ADDR + 0x47);
110
111 /* GP61 - LED_YELLOW */
112 outl(0x01, PME_IO_BASE_ADDR + 0x48);
113
114 /* GP3 */
115 outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
116
117 /* GP4 */
118 outl(0x04, PME_IO_BASE_ADDR + 0x4e);
119
120 /* FAN1 */
121 outl(0x01, PME_IO_BASE_ADDR + 0x56);
122
123 /* FAN2 */
124 outl(0x01, PME_IO_BASE_ADDR + 0x57);
125
126 /* Fan Control */
127 outl(0x50, PME_IO_BASE_ADDR + 0x58);
128
129 /* Fan1 Tachometer */
130 outl(0xff, PME_IO_BASE_ADDR + 0x59);
131
132 /* Fan2 Tachometer */
133 outl(0xff, PME_IO_BASE_ADDR + 0x5a);
134
135 /* LED1 */
136 outl(0x00, PME_IO_BASE_ADDR + 0x5d);
137
138 /* LED2 */
139 outl(0x00, PME_IO_BASE_ADDR + 0x5e);
140
141 /* Keyboard Scan Code */
142 outl(0x00, PME_IO_BASE_ADDR + 0x5f);
143
144 /* Exit the configuration state. */
145 outb(0xaa, port);
146}