Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | |
| 17 | #include <string.h> |
| 18 | #include <console/console.h> /* printk */ |
| 19 | #include "Platform.h" |
| 20 | #include "sb700_cfg.h" |
| 21 | |
| 22 | |
| 23 | /** |
| 24 | * @brief South Bridge CIMx configuration |
| 25 | * |
| 26 | * should be called before exeucte CIMx function. |
| 27 | * this function will be called in romstage and ramstage. |
| 28 | */ |
| 29 | void sb700_cimx_config(AMDSBCFG *sb_config) |
| 30 | { |
| 31 | if (!sb_config) { |
| 32 | printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n"); |
| 33 | return; |
| 34 | } |
| 35 | printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n"); |
| 36 | memset(sb_config, 0, sizeof(AMDSBCFG)); |
| 37 | |
| 38 | /* SB_POWERON_INIT */ |
| 39 | sb_config->StdHeader.Func = SB_POWERON_INIT; |
| 40 | |
| 41 | /* header */ |
| 42 | sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS; |
| 43 | |
| 44 | /* static Build Parameters */ |
| 45 | sb_config->BuildParameters.BiosSize = BIOS_SIZE; |
| 46 | sb_config->BuildParameters.LegacyFree = LEGACY_FREE; |
| 47 | sb_config->BuildParameters.EcKbd = 0; |
| 48 | sb_config->BuildParameters.EcChannel0 = 0; |
| 49 | sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; |
| 50 | sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; |
| 51 | sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; |
| 52 | sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; |
| 53 | sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; |
| 54 | |
| 55 | sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; |
| 56 | sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; |
| 57 | sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; |
| 58 | sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; |
| 59 | sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; |
| 60 | sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; |
| 61 | sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; |
| 62 | |
| 63 | sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; |
| 64 | sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; |
| 65 | sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; |
| 66 | sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; |
| 67 | sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID; |
| 68 | sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID; |
| 69 | sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID; |
| 70 | sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID; |
| 71 | sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; |
| 72 | sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID; |
| 73 | sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID; |
| 74 | sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; |
| 75 | sb_config->BuildParameters.IdeSsid = IDE_SSID; |
| 76 | sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; |
| 77 | sb_config->BuildParameters.LpcSsid = LPC_SSID; |
| 78 | |
| 79 | sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; |
| 80 | |
| 81 | /* General */ |
| 82 | sb_config->Spi33Mhz = 1; |
| 83 | sb_config->SpreadSpectrum = 0; |
| 84 | sb_config->PciClk5 = 0; |
| 85 | sb_config->PciClks = 0x1F; |
| 86 | sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood |
| 87 | sb_config->TimerClockSource = 2; // Auto |
| 88 | sb_config->S3Resume = 0; |
| 89 | sb_config->RebootRequired = 0; |
| 90 | |
| 91 | /* HPET */ |
| 92 | sb_config->HpetTimer = HPET_TIMER; |
| 93 | |
| 94 | /* USB */ |
| 95 | sb_config->UsbIntClock = 0; // Use external clock |
| 96 | sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 |
| 97 | sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 |
| 98 | sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 |
| 99 | sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 |
| 100 | sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 |
| 101 | sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 |
| 102 | sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 |
| 103 | sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable |
| 104 | |
| 105 | sb_config->AcpiS1Supported = 1; |
| 106 | |
| 107 | /* SATA */ |
| 108 | sb_config->SataController = 1; |
| 109 | sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci |
| 110 | sb_config->SataSmbus = 0; |
| 111 | sb_config->SataAggrLinkPmCap = 1; |
| 112 | sb_config->SataPortMultCap = 1; |
| 113 | sb_config->SataClkAutoOff = 1; |
| 114 | sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. |
| 115 | //TODO: set to secondary not take effect. |
| 116 | sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled |
| 117 | sb_config->SataEspPort = 0; |
| 118 | sb_config->SataClkAutoOffAhciMode = 1; |
| 119 | sb_config->SataHpcpButNonESP = 0; |
| 120 | sb_config->SataHideUnusedPort = 0; |
| 121 | |
| 122 | /* Azalia HDA */ |
| 123 | sb_config->AzaliaController = AZALIA_CONTROLLER; |
| 124 | sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; |
Bruce Griffith | 21d6fd9 | 2013-06-25 14:01:21 -0600 | [diff] [blame] | 125 | sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN_0; |
| 126 | sb_config->AzaliaSdin1 = AZALIA_SDIN_PIN_1; |
| 127 | sb_config->AzaliaSdin2 = AZALIA_SDIN_PIN_2; |
| 128 | sb_config->AzaliaSdin3 = AZALIA_SDIN_PIN_3; |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 129 | sb_config->pAzaliaOemCodecTablePtr = NULL; |
| 130 | |
| 131 | #ifndef __PRE_RAM__ |
| 132 | /* ramstage cimx config here */ |
| 133 | if (!sb_config->StdHeader.pCallBack) { |
| 134 | sb_config->StdHeader.pCallBack = sb700_callout_entry; |
| 135 | } |
| 136 | |
| 137 | //sb_config-> |
| 138 | #endif //!__PRE_RAM__ |
| 139 | printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n"); |
| 140 | } |