blob: 6a3b3c459487faa9f6f3571062cef6f746488ea5 [file] [log] [blame]
Werner Zehc42a6132015-02-12 12:40:15 +01001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Werner Zehc42a6132015-02-12 12:40:15 +010015
16if BOARD_SIEMENS_MC_TCU3
17
18config BOARD_SPECIFIC_OPTIONS # dummy
19 def_bool y
20 select SOC_INTEL_FSP_BAYTRAIL
21 select BOARD_ROMSIZE_KB_16384
22 select HAVE_ACPI_TABLES
23 select HAVE_OPTION_TABLE
Werner Zehc42a6132015-02-12 12:40:15 +010024 select ENABLE_BUILTIN_COM1
25 select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
26 select ENABLE_FSP_FAST_BOOT
27 select TSC_MONOTONIC_TIMER
28 select DRIVER_INTEL_I210
29 select SOC_INTEL_FSP_BAYTRAIL_MD
Werner Zeh538c6c92015-10-01 13:50:23 +020030 select USE_BLOBS
Werner Zeh2bb574e2016-01-22 06:45:59 +010031 select CBFS_AUTOGEN_ATTRIBUTES
Werner Zehbf13d3f2016-04-25 12:24:17 +020032 select USE_SIEMENS_HWILIB
Werner Zehc42a6132015-02-12 12:40:15 +010033
34config MAINBOARD_DIR
35 string
36 default "siemens/mc_tcu3"
37
Werner Zehc42a6132015-02-12 12:40:15 +010038config MAINBOARD_PART_NUMBER
39 string
40 default "MC_TCU3 (FSP)"
41
42
43config MAX_CPUS
44 int
45 default 16
46
47config CACHE_ROM_SIZE_OVERRIDE
48 hex
49 default 0x1000000
50
Werner Zehc42a6132015-02-12 12:40:15 +010051config CBFS_SIZE
52 hex
53 default 0x00e00000
54
55config FSP_PACKAGE_DEFAULT
56 bool "Configure defaults for the Intel FSP package"
57 default n
58
59config VGA_BIOS
60 bool
61 default y if FSP_PACKAGE_DEFAULT
62
63endif # BOARD_SIEMENS_MC_TCU3