Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | ## Foundation, Inc. |
Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 18 | ## |
| 19 | |
| 20 | if BOARD_SIEMENS_MC_TCU3 |
| 21 | |
| 22 | config BOARD_SPECIFIC_OPTIONS # dummy |
| 23 | def_bool y |
| 24 | select SOC_INTEL_FSP_BAYTRAIL |
| 25 | select BOARD_ROMSIZE_KB_16384 |
| 26 | select HAVE_ACPI_TABLES |
| 27 | select HAVE_OPTION_TABLE |
Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 28 | select ENABLE_BUILTIN_COM1 |
| 29 | select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT |
| 30 | select ENABLE_FSP_FAST_BOOT |
| 31 | select TSC_MONOTONIC_TIMER |
| 32 | select DRIVER_INTEL_I210 |
| 33 | select SOC_INTEL_FSP_BAYTRAIL_MD |
Werner Zeh | 538c6c9 | 2015-10-01 13:50:23 +0200 | [diff] [blame^] | 34 | select USE_BLOBS |
Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 35 | |
| 36 | config MAINBOARD_DIR |
| 37 | string |
| 38 | default "siemens/mc_tcu3" |
| 39 | |
Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 40 | config MAINBOARD_PART_NUMBER |
| 41 | string |
| 42 | default "MC_TCU3 (FSP)" |
| 43 | |
| 44 | |
| 45 | config MAX_CPUS |
| 46 | int |
| 47 | default 16 |
| 48 | |
| 49 | config CACHE_ROM_SIZE_OVERRIDE |
| 50 | hex |
| 51 | default 0x1000000 |
| 52 | |
Werner Zeh | c42a613 | 2015-02-12 12:40:15 +0100 | [diff] [blame] | 53 | config CBFS_SIZE |
| 54 | hex |
| 55 | default 0x00e00000 |
| 56 | |
| 57 | config FSP_PACKAGE_DEFAULT |
| 58 | bool "Configure defaults for the Intel FSP package" |
| 59 | default n |
| 60 | |
| 61 | config VGA_BIOS |
| 62 | bool |
| 63 | default y if FSP_PACKAGE_DEFAULT |
| 64 | |
| 65 | endif # BOARD_SIEMENS_MC_TCU3 |