Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include "AGESA.h" |
| 17 | #include "amdlib.h" |
| 18 | #include "Ids.h" |
| 19 | #include "heapManager.h" |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 20 | #include <PlatformMemoryConfiguration.h> |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 21 | #include "PlatformGnbPcieComplex.h" |
| 22 | #include "Filecode.h" |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 23 | |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 24 | #include <string.h> |
Kyösti Mälkki | 34ad72c | 2014-10-21 13:43:46 +0300 | [diff] [blame] | 25 | #include <northbridge/amd/agesa/agesawrapper.h> |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 26 | |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 27 | #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE |
| 28 | |
| 29 | /*---------------------------------------------------------------------------------------*/ |
| 30 | /** |
| 31 | * OemCustomizeInitEarly |
| 32 | * |
| 33 | * Description: |
| 34 | * This stub function will call the host environment through the binary block |
| 35 | * interface (call-out port) to provide a user hook opportunity |
| 36 | * |
| 37 | * Parameters: |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 38 | * @param[in] *InitEarly |
| 39 | * |
| 40 | * @retval VOID |
| 41 | * |
| 42 | **/ |
| 43 | /*---------------------------------------------------------------------------------------*/ |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 44 | |
| 45 | static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 46 | { |
| 47 | AGESA_STATUS Status; |
| 48 | VOID *BrazosPcieComplexListPtr; |
| 49 | VOID *BrazosPciePortPtr; |
| 50 | VOID *BrazosPcieDdiPtr; |
| 51 | |
| 52 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 53 | |
| 54 | PCIe_PORT_DESCRIPTOR PortList [] = { |
| 55 | // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) |
| 56 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 57 | 0, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 58 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), |
Jens Rottmann | 68c9f2b | 2013-03-01 17:20:42 +0100 | [diff] [blame] | 59 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 60 | }, |
| 61 | // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) |
| 62 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 63 | 0, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 64 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), |
Jens Rottmann | 68c9f2b | 2013-03-01 17:20:42 +0100 | [diff] [blame] | 65 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 66 | }, |
| 67 | // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) |
| 68 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 69 | 0, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 70 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), |
Jens Rottmann | 68c9f2b | 2013-03-01 17:20:42 +0100 | [diff] [blame] | 71 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 72 | }, |
| 73 | // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) |
| 74 | { |
| 75 | 0, |
| 76 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), |
| 77 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) |
| 78 | }, |
| 79 | // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) |
| 80 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 81 | DESCRIPTOR_TERMINATE_LIST, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 82 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), |
| 83 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) |
| 84 | } |
| 85 | }; |
| 86 | |
| 87 | PCIe_DDI_DESCRIPTOR DdiList [] = { |
| 88 | // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) |
| 89 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 90 | 0, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 91 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), |
| 92 | //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) |
Jens Rottmann | 68c9f2b | 2013-03-01 17:20:42 +0100 | [diff] [blame] | 93 | {ConnectorTypeAutoDetect, Aux1, Hdp1} |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 94 | }, |
| 95 | // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) |
| 96 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame] | 97 | DESCRIPTOR_TERMINATE_LIST, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 98 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), |
| 99 | //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) |
Jens Rottmann | 68c9f2b | 2013-03-01 17:20:42 +0100 | [diff] [blame] | 100 | {ConnectorTypeAutoDetect, Aux2, Hdp2} |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 101 | } |
| 102 | }; |
| 103 | |
| 104 | PCIe_COMPLEX_DESCRIPTOR Brazos = { |
| 105 | DESCRIPTOR_TERMINATE_LIST, |
| 106 | 0, |
| 107 | &PortList[0], |
| 108 | &DdiList[0] |
| 109 | }; |
| 110 | |
| 111 | // GNB PCIe topology Porting |
| 112 | |
| 113 | // |
| 114 | // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR |
| 115 | // |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 116 | AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 117 | |
| 118 | AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; |
| 119 | AllocHeapParams.Persist = HEAP_LOCAL_CACHE; |
| 120 | Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); |
Kyösti Mälkki | 1ef67e1 | 2014-12-16 16:45:52 +0200 | [diff] [blame] | 121 | ASSERT(Status == AGESA_SUCCESS); |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 122 | |
| 123 | BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
| 124 | |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 125 | AllocHeapParams.BufferPtr += sizeof(Brazos); |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 126 | BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; |
| 127 | |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 128 | AllocHeapParams.BufferPtr += sizeof(PortList); |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 129 | BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
| 130 | |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 131 | memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); |
| 132 | memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); |
| 133 | memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 134 | |
| 135 | |
| 136 | ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; |
| 137 | ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; |
| 138 | |
| 139 | InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; |
| 140 | InitEarly->GnbConfig.PsppPolicy = 0; |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 141 | return AGESA_SUCCESS; |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 142 | } |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 143 | |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 144 | /*---------------------------------------------------------------------------------------- |
| 145 | * CUSTOMER OVERIDES MEMORY TABLE |
| 146 | *---------------------------------------------------------------------------------------- |
| 147 | */ |
| 148 | |
| 149 | /* |
| 150 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA |
| 151 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable |
| 152 | * is populated, AGESA will base its settings on the data from the table. Otherwise, it will |
| 153 | * use its default conservative settings. |
| 154 | */ |
| 155 | CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { |
| 156 | HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B), |
| 157 | NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), |
| 158 | NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), |
| 159 | PSO_END |
| 160 | }; |
| 161 | |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 162 | const struct OEM_HOOK OemCustomize = { |
| 163 | .InitEarly = OemInitEarly, |
| 164 | }; |