Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | * Foundation, Inc. |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include "AGESA.h" |
| 21 | #include "amdlib.h" |
| 22 | #include "Ids.h" |
| 23 | #include "heapManager.h" |
| 24 | #include "PlatformGnbPcieComplex.h" |
| 25 | #include "Filecode.h" |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 26 | |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 27 | #include <string.h> |
Kyösti Mälkki | 34ad72c | 2014-10-21 13:43:46 +0300 | [diff] [blame] | 28 | #include <northbridge/amd/agesa/agesawrapper.h> |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 29 | |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 30 | #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE |
| 31 | |
| 32 | /*---------------------------------------------------------------------------------------*/ |
| 33 | /** |
| 34 | * OemCustomizeInitEarly |
| 35 | * |
| 36 | * Description: |
| 37 | * This stub function will call the host environment through the binary block |
| 38 | * interface (call-out port) to provide a user hook opportunity |
| 39 | * |
| 40 | * Parameters: |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 41 | * @param[in] *InitEarly |
| 42 | * |
| 43 | * @retval VOID |
| 44 | * |
| 45 | **/ |
| 46 | /*---------------------------------------------------------------------------------------*/ |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 47 | |
| 48 | static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 49 | { |
| 50 | AGESA_STATUS Status; |
| 51 | VOID *BrazosPcieComplexListPtr; |
| 52 | VOID *BrazosPciePortPtr; |
| 53 | VOID *BrazosPcieDdiPtr; |
| 54 | |
| 55 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 56 | |
| 57 | PCIe_PORT_DESCRIPTOR PortList [] = { |
| 58 | // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) |
| 59 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame^] | 60 | 0, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 61 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), |
Jens Rottmann | 68c9f2b | 2013-03-01 17:20:42 +0100 | [diff] [blame] | 62 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 63 | }, |
| 64 | // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) |
| 65 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame^] | 66 | 0, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 67 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), |
Jens Rottmann | 68c9f2b | 2013-03-01 17:20:42 +0100 | [diff] [blame] | 68 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 69 | }, |
| 70 | // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) |
| 71 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame^] | 72 | 0, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 73 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), |
Jens Rottmann | 68c9f2b | 2013-03-01 17:20:42 +0100 | [diff] [blame] | 74 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 75 | }, |
| 76 | // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) |
| 77 | { |
| 78 | 0, |
| 79 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), |
| 80 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) |
| 81 | }, |
| 82 | // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) |
| 83 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame^] | 84 | DESCRIPTOR_TERMINATE_LIST, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 85 | PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), |
| 86 | PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) |
| 87 | } |
| 88 | }; |
| 89 | |
| 90 | PCIe_DDI_DESCRIPTOR DdiList [] = { |
| 91 | // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) |
| 92 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame^] | 93 | 0, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 94 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), |
| 95 | //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) |
Jens Rottmann | 68c9f2b | 2013-03-01 17:20:42 +0100 | [diff] [blame] | 96 | {ConnectorTypeAutoDetect, Aux1, Hdp1} |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 97 | }, |
| 98 | // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) |
| 99 | { |
Kyösti Mälkki | 9d035fa | 2015-05-23 14:27:44 +0300 | [diff] [blame^] | 100 | DESCRIPTOR_TERMINATE_LIST, |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 101 | PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), |
| 102 | //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) |
Jens Rottmann | 68c9f2b | 2013-03-01 17:20:42 +0100 | [diff] [blame] | 103 | {ConnectorTypeAutoDetect, Aux2, Hdp2} |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 104 | } |
| 105 | }; |
| 106 | |
| 107 | PCIe_COMPLEX_DESCRIPTOR Brazos = { |
| 108 | DESCRIPTOR_TERMINATE_LIST, |
| 109 | 0, |
| 110 | &PortList[0], |
| 111 | &DdiList[0] |
| 112 | }; |
| 113 | |
| 114 | // GNB PCIe topology Porting |
| 115 | |
| 116 | // |
| 117 | // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR |
| 118 | // |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 119 | AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 120 | |
| 121 | AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; |
| 122 | AllocHeapParams.Persist = HEAP_LOCAL_CACHE; |
| 123 | Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); |
Kyösti Mälkki | 1ef67e1 | 2014-12-16 16:45:52 +0200 | [diff] [blame] | 124 | ASSERT(Status == AGESA_SUCCESS); |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 125 | |
| 126 | BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
| 127 | |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 128 | AllocHeapParams.BufferPtr += sizeof(Brazos); |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 129 | BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; |
| 130 | |
Paul Menzel | d189229 | 2013-05-14 10:06:47 +0200 | [diff] [blame] | 131 | AllocHeapParams.BufferPtr += sizeof(PortList); |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 132 | BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; |
| 133 | |
Edward O'Callaghan | 8864e1c | 2014-04-30 23:13:08 +1000 | [diff] [blame] | 134 | memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); |
| 135 | memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); |
| 136 | memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 137 | |
| 138 | |
| 139 | ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; |
| 140 | ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; |
| 141 | |
| 142 | InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; |
| 143 | InitEarly->GnbConfig.PsppPolicy = 0; |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 144 | return AGESA_SUCCESS; |
Jens Rottmann | 1664404 | 2013-03-01 17:12:56 +0100 | [diff] [blame] | 145 | } |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 146 | |
| 147 | const struct OEM_HOOK OemCustomize = { |
| 148 | .InitEarly = OemInitEarly, |
| 149 | }; |