blob: a1cf338161670a750a949b23f0cd521bb2f3cb63 [file] [log] [blame]
Edward O'Callaghan32960e32014-11-23 17:38:52 +11001#
2# This file is part of the coreboot project.
3#
4# Copyright (C) 2012 Advanced Micro Devices, Inc.
5#
6# This program is free software; you can redistribute it and/or modify
7# it under the terms of the GNU General Public License as published by
8# the Free Software Foundation; version 2 of the License.
9#
10# This program is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
Edward O'Callaghan32960e32014-11-23 17:38:52 +110015chip northbridge/amd/agesa/family15rl/root_complex
16
17 device cpu_cluster 0 on
18 chip cpu/amd/agesa/family15rl
19 device lapic 10 on end
20 end
21 end
22
23 device domain 0 on
24 subsystemid 0x1022 0x1410 inherit
25 chip northbridge/amd/agesa/family15rl # CPU side of HT root complex
26
27 chip northbridge/amd/agesa/family15rl # PCI side of HT root complex
28 device pci 0.0 on end # Root Complex
Edward O'Callaghan14581fc62014-12-05 04:25:44 +110029 device pci 0.2 on end # IOMMU
Edward O'Callaghan32960e32014-11-23 17:38:52 +110030 device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
31 device pci 1.1 on end # Internal Multimedia
32 device pci 2.0 off end
33 device pci 3.0 off end
34 device pci 4.0 on end # PCIE MINI0
35 device pci 5.0 on end # PCIE MINI1
36 device pci 6.0 off end #
37 device pci 7.0 off end #
38 device pci 8.0 off end # NB/SB Link P2P bridge ?
39 device pci 9.0 off end #
40 end #chip northbridge/amd/agesa/family15rl # PCI side of HT root complex
41
42 chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
43 device pci 10.0 off end # FCH USB XHCI Controller HC0 (N.B. breaks EHCI debug!!!)
44 device pci 11.0 on end # FCH SATA Controller [AHCI mode]
45 device pci 12.0 on end # FCH USB OHCI Controller
46 device pci 12.2 on end # FCH USB EHCI Controller
47 device pci 13.0 on end # FCH USB OHCI Controller
48 device pci 13.2 on end # FCH USB EHCI Controller
49 device pci 14.0 on # SMBUS
50 chip drivers/generic/generic #dimm 0
51 device i2c 50 on end # 7-bit SPD address
52 end
53 chip drivers/generic/generic #dimm 1
54 device i2c 51 on end # 7-bit SPD address
55 end
56 end # SM
Edward O'Callaghan58b532d2014-11-28 02:53:32 +110057 device pci 14.2 on end # FCH Azalia Controller
58 device pci 14.3 on # FCH LPC Bridge [1022:780e]
Edward O'Callaghan32960e32014-11-23 17:38:52 +110059 chip ec/compal/ene932
60 # 60/64 KBC
61 device pnp ff.1 on end # dummy address
62 end
63 end
Edward O'Callaghan32960e32014-11-23 17:38:52 +110064 device pci 14.4 on end # FCH PCI Bridge [1022:780f]
65 device pci 14.5 off end # USB 2
66 device pci 14.6 off end # Gec
67 device pci 14.7 off end # SD
68 device pci 15.0 off end # PCIe 0
69 device pci 15.1 off end # PCIe 1
70 device pci 15.2 off end # PCIe 2
71 device pci 15.3 off end # PCIe 3
Marshall Dawsonf5d9d142016-12-16 12:53:53 -050072 end #chip southbridge/amd/agesa/hudson
Edward O'Callaghan32960e32014-11-23 17:38:52 +110073
74 device pci 18.0 on end
75 device pci 18.1 on end
76 device pci 18.2 on end
77 device pci 18.3 on end
78 device pci 18.4 on end
79 device pci 18.5 on end
80
81 register "spdAddrLookup" = "
82 {
83 { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
84 { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
85 }"
86
87 end #chip northbridge/amd/agesa/family15rl # CPU side of HT root complex
88 end #domain
89end #chip northbridge/amd/agesa/family15rl/root_complex