Edward O'Callaghan | 32960e3 | 2014-11-23 17:38:52 +1100 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
| 15 | # You should have received a copy of the GNU General Public License |
| 16 | # along with this program; if not, write to the Free Software |
| 17 | # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | # |
| 19 | chip northbridge/amd/agesa/family15rl/root_complex |
| 20 | |
| 21 | device cpu_cluster 0 on |
| 22 | chip cpu/amd/agesa/family15rl |
| 23 | device lapic 10 on end |
| 24 | end |
| 25 | end |
| 26 | |
| 27 | device domain 0 on |
| 28 | subsystemid 0x1022 0x1410 inherit |
| 29 | chip northbridge/amd/agesa/family15rl # CPU side of HT root complex |
| 30 | |
| 31 | chip northbridge/amd/agesa/family15rl # PCI side of HT root complex |
| 32 | device pci 0.0 on end # Root Complex |
| 33 | device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX |
| 34 | device pci 1.1 on end # Internal Multimedia |
| 35 | device pci 2.0 off end |
| 36 | device pci 3.0 off end |
| 37 | device pci 4.0 on end # PCIE MINI0 |
| 38 | device pci 5.0 on end # PCIE MINI1 |
| 39 | device pci 6.0 off end # |
| 40 | device pci 7.0 off end # |
| 41 | device pci 8.0 off end # NB/SB Link P2P bridge ? |
| 42 | device pci 9.0 off end # |
| 43 | end #chip northbridge/amd/agesa/family15rl # PCI side of HT root complex |
| 44 | |
| 45 | chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus |
| 46 | device pci 10.0 off end # FCH USB XHCI Controller HC0 (N.B. breaks EHCI debug!!!) |
| 47 | device pci 11.0 on end # FCH SATA Controller [AHCI mode] |
| 48 | device pci 12.0 on end # FCH USB OHCI Controller |
| 49 | device pci 12.2 on end # FCH USB EHCI Controller |
| 50 | device pci 13.0 on end # FCH USB OHCI Controller |
| 51 | device pci 13.2 on end # FCH USB EHCI Controller |
| 52 | device pci 14.0 on # SMBUS |
| 53 | chip drivers/generic/generic #dimm 0 |
| 54 | device i2c 50 on end # 7-bit SPD address |
| 55 | end |
| 56 | chip drivers/generic/generic #dimm 1 |
| 57 | device i2c 51 on end # 7-bit SPD address |
| 58 | end |
| 59 | end # SM |
Edward O'Callaghan | 58b532d | 2014-11-28 02:53:32 +1100 | [diff] [blame^] | 60 | device pci 14.2 on end # FCH Azalia Controller |
| 61 | device pci 14.3 on # FCH LPC Bridge [1022:780e] |
Edward O'Callaghan | 32960e3 | 2014-11-23 17:38:52 +1100 | [diff] [blame] | 62 | chip ec/compal/ene932 |
| 63 | # 60/64 KBC |
| 64 | device pnp ff.1 on end # dummy address |
| 65 | end |
| 66 | end |
Edward O'Callaghan | 32960e3 | 2014-11-23 17:38:52 +1100 | [diff] [blame] | 67 | device pci 14.4 on end # FCH PCI Bridge [1022:780f] |
| 68 | device pci 14.5 off end # USB 2 |
| 69 | device pci 14.6 off end # Gec |
| 70 | device pci 14.7 off end # SD |
| 71 | device pci 15.0 off end # PCIe 0 |
| 72 | device pci 15.1 off end # PCIe 1 |
| 73 | device pci 15.2 off end # PCIe 2 |
| 74 | device pci 15.3 off end # PCIe 3 |
| 75 | register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE |
| 76 | register "gpp_configuration" = "4" |
| 77 | end #chip southbridge/amd/hudson |
| 78 | |
| 79 | device pci 18.0 on end |
| 80 | device pci 18.1 on end |
| 81 | device pci 18.2 on end |
| 82 | device pci 18.3 on end |
| 83 | device pci 18.4 on end |
| 84 | device pci 18.5 on end |
| 85 | |
| 86 | register "spdAddrLookup" = " |
| 87 | { |
| 88 | { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| 89 | { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses |
| 90 | }" |
| 91 | |
| 92 | end #chip northbridge/amd/agesa/family15rl # CPU side of HT root complex |
| 93 | end #domain |
| 94 | end #chip northbridge/amd/agesa/family15rl/root_complex |