blob: c6c9b52de92b976351ffdd0225d10d57946250fb [file] [log] [blame]
Lee Leahy5cb9dda2015-05-01 10:34:54 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Google Inc.
5 * Copyright (C) 2015 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy5cb9dda2015-05-01 10:34:54 -070015 */
16
17#include <arch/acpi.h>
18#include <arch/acpigen.h>
19#include <arch/ioapic.h>
20#include <arch/smp/mpspec.h>
21#include <cbmem.h>
22#include <console/console.h>
Lee Leahy5cb9dda2015-05-01 10:34:54 -070023#include <device/device.h>
24#include <device/pci.h>
25#include <device/pci_ids.h>
26#include <soc/acpi.h>
27#include <soc/iomap.h>
28#include <soc/nvs.h>
29#include <string.h>
30#include <types.h>
31#include <boardid.h>
32#include "onboard.h"
33
34void acpi_create_gnvs(global_nvs_t *gnvs)
35{
36 acpi_init_gnvs(gnvs);
37
38 /* Enable USB ports in S3 */
39 gnvs->s3u0 = 1;
40 gnvs->s3u1 = 1;
41
42 /* Disable USB ports in S5 */
43 gnvs->s5u0 = 0;
44 gnvs->s5u1 = 0;
45
46 /* Enable DPTF */
47 gnvs->dpte = 1;
Hannah Williams103f00d2016-01-25 14:36:56 -080048
49 /* PMIC is configured in I2C1, hidden it from OS */
50 gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;
Lee Leahy5cb9dda2015-05-01 10:34:54 -070051}
52
53unsigned long acpi_fill_madt(unsigned long current)
54{
55 /* Local APICs */
56 current = acpi_create_madt_lapics(current);
57
58 /* IOAPIC */
59 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
60 2, IO_APIC_ADDR, 0);
61
62 current = acpi_madt_irq_overrides(current);
63
64 return current;
65}