blob: 47c89339c0a71d67b6a8a4005ed06d8a76d362cb [file] [log] [blame]
Lee Leahy5cb9dda2015-05-01 10:34:54 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Google Inc.
5 * Copyright (C) 2015 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.
19 */
20
21#include <arch/acpi.h>
22#include <arch/acpigen.h>
23#include <arch/ioapic.h>
24#include <arch/smp/mpspec.h>
25#include <cbmem.h>
26#include <console/console.h>
27#include <cpu/cpu.h>
28#include <cpu/x86/msr.h>
29#include <device/device.h>
30#include <device/pci.h>
31#include <device/pci_ids.h>
32#include <soc/acpi.h>
33#include <soc/iomap.h>
34#include <soc/nvs.h>
35#include <string.h>
36#include <types.h>
37#include <boardid.h>
38#include "onboard.h"
39
40void acpi_create_gnvs(global_nvs_t *gnvs)
41{
42 acpi_init_gnvs(gnvs);
43
44 /* Enable USB ports in S3 */
45 gnvs->s3u0 = 1;
46 gnvs->s3u1 = 1;
47
48 /* Disable USB ports in S5 */
49 gnvs->s5u0 = 0;
50 gnvs->s5u1 = 0;
51
52 /* Enable DPTF */
53 gnvs->dpte = 1;
54 if (board_id() == BOARD_BCRD2)
55 gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;
56}
57
58unsigned long acpi_fill_madt(unsigned long current)
59{
60 /* Local APICs */
61 current = acpi_create_madt_lapics(current);
62
63 /* IOAPIC */
64 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
65 2, IO_APIC_ADDR, 0);
66
67 current = acpi_madt_irq_overrides(current);
68
69 return current;
70}