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review.coreboot.org / coreboot / a50ced2eba20a007fa5b486c251c252ad09868cf / . / src / mainboard / intel / minnow3 / romstage.c
blob: 451e7b4739fac970f0cdabb81f213f0aa4532429 [file] [log] [blame]
Brenton Dong35f03d92017-02-06 16:07:27 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <string.h>
17#include <soc/romstage.h>
18#include <fsp/api.h>
19#include <FspmUpd.h>
Brenton Dong35f03d92017-02-06 16:07:27 -0700[diff] [blame]20
21static const uint8_t Ch0_Bit_swizzling[] = {
22 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f,
23 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03,
24 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e,
25 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15
26};
27static const uint8_t Ch1_Bit_swizzling[] = {
28 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02,
29 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f,
30 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17,
31 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f
32};
33static const uint8_t Ch2_Bit_swizzling[] = {
34 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a,
35 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04,
36 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d,
37 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11
38};
39static const uint8_t Ch3_Bit_swizzling[] = {
40 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07,
41 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d,
42 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12,
43 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f
44};
45
46void mainboard_memory_init_params(FSPM_UPD *memupd)
47{
Brenton Dong35f03d92017-02-06 16:07:27 -0700[diff] [blame]48 /* DRAM Config settings */
49 memupd->FspmConfig.Package = 0x1;
50 memupd->FspmConfig.Profile = 0xB;
51 memupd->FspmConfig.MemoryDown = 0x1;
52 memupd->FspmConfig.DDR3LPageSize = 0x0;
53 memupd->FspmConfig.DDR3LASR = 0x0;
54 memupd->FspmConfig.ScramblerSupport = 0x1;
55 memupd->FspmConfig.ChannelHashMask = 0x36;
56 memupd->FspmConfig.SliceHashMask = 0x9;
57 memupd->FspmConfig.InterleavedMode = 0x2;
58 memupd->FspmConfig.ChannelsSlicesEnable = 0x0;
59 memupd->FspmConfig.MinRefRate2xEnable = 0x0;
Brenton Dong97f542e2017-02-15 11:50:02 -0700[diff] [blame]60 memupd->FspmConfig.DualRankSupportEnable = 0x0;
Brenton Dong35f03d92017-02-06 16:07:27 -0700[diff] [blame]61 memupd->FspmConfig.RmtMode = 0x0;
62 memupd->FspmConfig.MemorySizeLimit = 0x1800;
63 memupd->FspmConfig.LowMemoryMaxValue = 0x0;
64 memupd->FspmConfig.DisableFastBoot = 0x0;
65 memupd->FspmConfig.HighMemoryMaxValue = 0x0;
66 memupd->FspmConfig.DIMM0SPDAddress = 0x0;
67 memupd->FspmConfig.DIMM1SPDAddress = 0x0;
Brenton Dong97f542e2017-02-15 11:50:02 -0700[diff] [blame]68 memupd->FspmConfig.Ch0_RankEnable = 0x1;
Brenton Dong35f03d92017-02-06 16:07:27 -0700[diff] [blame]69 memupd->FspmConfig.Ch0_DeviceWidth = 0x1;
70 memupd->FspmConfig.Ch0_DramDensity = 0x2;
71 memupd->FspmConfig.Ch0_Option = 0x3;
72 memupd->FspmConfig.Ch0_OdtConfig = 0x0;
73 memupd->FspmConfig.Ch0_TristateClk1 = 0x0;
74 memupd->FspmConfig.Ch0_Mode2N = 0x0;
75 memupd->FspmConfig.Ch0_OdtLevels = 0x0;
Brenton Dong97f542e2017-02-15 11:50:02 -0700[diff] [blame]76 memupd->FspmConfig.Ch1_RankEnable = 0x1;
Brenton Dong35f03d92017-02-06 16:07:27 -0700[diff] [blame]77 memupd->FspmConfig.Ch1_DeviceWidth = 0x1;
78 memupd->FspmConfig.Ch1_DramDensity = 0x2;
79 memupd->FspmConfig.Ch1_Option = 0x3;
80 memupd->FspmConfig.Ch1_OdtConfig = 0x0;
81 memupd->FspmConfig.Ch1_TristateClk1 = 0x0;
82 memupd->FspmConfig.Ch1_Mode2N = 0x0;
83 memupd->FspmConfig.Ch1_OdtLevels = 0x0;
Brenton Dong97f542e2017-02-15 11:50:02 -0700[diff] [blame]84 memupd->FspmConfig.Ch2_RankEnable = 0x1;
Brenton Dong35f03d92017-02-06 16:07:27 -0700[diff] [blame]85 memupd->FspmConfig.Ch2_DeviceWidth = 0x1;
86 memupd->FspmConfig.Ch2_DramDensity = 0x2;
87 memupd->FspmConfig.Ch2_Option = 0x3;
88 memupd->FspmConfig.Ch2_OdtConfig = 0x0;
89 memupd->FspmConfig.Ch2_TristateClk1 = 0x0;
90 memupd->FspmConfig.Ch2_Mode2N = 0x0;
91 memupd->FspmConfig.Ch2_OdtLevels = 0x0;
Brenton Dong97f542e2017-02-15 11:50:02 -0700[diff] [blame]92 memupd->FspmConfig.Ch3_RankEnable = 0x1;
Brenton Dong35f03d92017-02-06 16:07:27 -0700[diff] [blame]93 memupd->FspmConfig.Ch3_DeviceWidth = 0x1;
94 memupd->FspmConfig.Ch3_DramDensity = 0x2;
95 memupd->FspmConfig.Ch3_Option = 0x3;
96 memupd->FspmConfig.Ch3_OdtConfig = 0x0;
97 memupd->FspmConfig.Ch3_TristateClk1 = 0x0;
98 memupd->FspmConfig.Ch3_Mode2N = 0x0;
99 memupd->FspmConfig.Ch3_OdtLevels = 0x0;
100 memupd->FspmConfig.RmtCheckRun = 0x0;
101 memupd->FspmConfig.MrcDataSaving = 0x0;
102 memupd->FspmConfig.MrcFastBoot = 0x0;
103
104 memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,
105 sizeof(Ch0_Bit_swizzling));
106 memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling,
107 sizeof(Ch1_Bit_swizzling));
108 memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling,
109 sizeof(Ch2_Bit_swizzling));
110 memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,
111 sizeof(Ch3_Bit_swizzling));
112
113 memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0;
114 memupd->FspmConfig.MsgLevelMask = 0x0;
115}