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Brenton Dong35f03d92017-02-06 16:07:27 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <string.h>
17#include <soc/romstage.h>
18#include <fsp/api.h>
19#include <FspmUpd.h>
20#include "brd_gpio.h"
21
22static const uint8_t Ch0_Bit_swizzling[] = {
23 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f,
24 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03,
25 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e,
26 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15
27};
28static const uint8_t Ch1_Bit_swizzling[] = {
29 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02,
30 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f,
31 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17,
32 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f
33};
34static const uint8_t Ch2_Bit_swizzling[] = {
35 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a,
36 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04,
37 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d,
38 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11
39};
40static const uint8_t Ch3_Bit_swizzling[] = {
41 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07,
42 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d,
43 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12,
44 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f
45};
46
47void mainboard_memory_init_params(FSPM_UPD *memupd)
48{
49 /* setup early gpio before memory */
50 gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
51
52 /* DRAM Config settings */
53 memupd->FspmConfig.Package = 0x1;
54 memupd->FspmConfig.Profile = 0xB;
55 memupd->FspmConfig.MemoryDown = 0x1;
56 memupd->FspmConfig.DDR3LPageSize = 0x0;
57 memupd->FspmConfig.DDR3LASR = 0x0;
58 memupd->FspmConfig.ScramblerSupport = 0x1;
59 memupd->FspmConfig.ChannelHashMask = 0x36;
60 memupd->FspmConfig.SliceHashMask = 0x9;
61 memupd->FspmConfig.InterleavedMode = 0x2;
62 memupd->FspmConfig.ChannelsSlicesEnable = 0x0;
63 memupd->FspmConfig.MinRefRate2xEnable = 0x0;
64 memupd->FspmConfig.DualRankSupportEnable = 0x1;
65 memupd->FspmConfig.RmtMode = 0x0;
66 memupd->FspmConfig.MemorySizeLimit = 0x1800;
67 memupd->FspmConfig.LowMemoryMaxValue = 0x0;
68 memupd->FspmConfig.DisableFastBoot = 0x0;
69 memupd->FspmConfig.HighMemoryMaxValue = 0x0;
70 memupd->FspmConfig.DIMM0SPDAddress = 0x0;
71 memupd->FspmConfig.DIMM1SPDAddress = 0x0;
72 memupd->FspmConfig.Ch0_RankEnable = 0x3;
73 memupd->FspmConfig.Ch0_DeviceWidth = 0x1;
74 memupd->FspmConfig.Ch0_DramDensity = 0x2;
75 memupd->FspmConfig.Ch0_Option = 0x3;
76 memupd->FspmConfig.Ch0_OdtConfig = 0x0;
77 memupd->FspmConfig.Ch0_TristateClk1 = 0x0;
78 memupd->FspmConfig.Ch0_Mode2N = 0x0;
79 memupd->FspmConfig.Ch0_OdtLevels = 0x0;
80 memupd->FspmConfig.Ch1_RankEnable = 0x3;
81 memupd->FspmConfig.Ch1_DeviceWidth = 0x1;
82 memupd->FspmConfig.Ch1_DramDensity = 0x2;
83 memupd->FspmConfig.Ch1_Option = 0x3;
84 memupd->FspmConfig.Ch1_OdtConfig = 0x0;
85 memupd->FspmConfig.Ch1_TristateClk1 = 0x0;
86 memupd->FspmConfig.Ch1_Mode2N = 0x0;
87 memupd->FspmConfig.Ch1_OdtLevels = 0x0;
88 memupd->FspmConfig.Ch2_RankEnable = 0x3;
89 memupd->FspmConfig.Ch2_DeviceWidth = 0x1;
90 memupd->FspmConfig.Ch2_DramDensity = 0x2;
91 memupd->FspmConfig.Ch2_Option = 0x3;
92 memupd->FspmConfig.Ch2_OdtConfig = 0x0;
93 memupd->FspmConfig.Ch2_TristateClk1 = 0x0;
94 memupd->FspmConfig.Ch2_Mode2N = 0x0;
95 memupd->FspmConfig.Ch2_OdtLevels = 0x0;
96 memupd->FspmConfig.Ch3_RankEnable = 0x3;
97 memupd->FspmConfig.Ch3_DeviceWidth = 0x1;
98 memupd->FspmConfig.Ch3_DramDensity = 0x2;
99 memupd->FspmConfig.Ch3_Option = 0x3;
100 memupd->FspmConfig.Ch3_OdtConfig = 0x0;
101 memupd->FspmConfig.Ch3_TristateClk1 = 0x0;
102 memupd->FspmConfig.Ch3_Mode2N = 0x0;
103 memupd->FspmConfig.Ch3_OdtLevels = 0x0;
104 memupd->FspmConfig.RmtCheckRun = 0x0;
105 memupd->FspmConfig.MrcDataSaving = 0x0;
106 memupd->FspmConfig.MrcFastBoot = 0x0;
107
108 memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,
109 sizeof(Ch0_Bit_swizzling));
110 memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling,
111 sizeof(Ch1_Bit_swizzling));
112 memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling,
113 sizeof(Ch2_Bit_swizzling));
114 memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,
115 sizeof(Ch3_Bit_swizzling));
116
117 memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0;
118 memupd->FspmConfig.MsgLevelMask = 0x0;
119}