Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <arch/io.h> |
Uwe Hermann | 74d1a6e | 2010-10-12 17:34:08 +0000 | [diff] [blame] | 20 | #include <arch/ioapic.h> |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 21 | #include <arch/smp/mpspec.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <string.h> |
| 24 | #include <stdint.h> |
| 25 | |
| 26 | // Generate MP-table IRQ numbers for PCI devices. |
| 27 | #define IO_APIC0 2 |
| 28 | |
| 29 | #define INT_A 0 |
| 30 | #define INT_B 1 |
| 31 | #define INT_C 2 |
| 32 | #define INT_D 3 |
| 33 | #define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine) |
| 34 | |
| 35 | #define PIRQ_A 16 |
| 36 | #define PIRQ_B 17 |
| 37 | #define PIRQ_C 18 |
| 38 | #define PIRQ_D 19 |
| 39 | #define PIRQ_E 20 |
| 40 | #define PIRQ_F 21 |
| 41 | #define PIRQ_G 22 |
| 42 | #define PIRQ_H 23 |
| 43 | |
| 44 | // RCBA |
| 45 | #define RCBA 0xF0 |
| 46 | |
| 47 | #define RCBA_D31IP 0x3100 |
| 48 | #define RCBA_D30IP 0x3104 |
| 49 | #define RCBA_D29IP 0x3108 |
| 50 | #define RCBA_D28IP 0x310C |
| 51 | #define RCBA_D31IR 0x3140 |
| 52 | #define RCBA_D30IR 0x3142 |
| 53 | #define RCBA_D29IR 0x3144 |
| 54 | #define RCBA_D28IR 0x3146 |
| 55 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 56 | static void *smp_write_config_table(void *v) |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 57 | { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 58 | struct mp_config_table *mc; |
Patrick Georgi | 7411eab | 2010-11-22 14:14:56 +0000 | [diff] [blame] | 59 | unsigned char bus_chipset, bus_pci; |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 60 | unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b; |
Patrick Georgi | 7411eab | 2010-11-22 14:14:56 +0000 | [diff] [blame] | 61 | int bus_isa, i; |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 62 | uint32_t pin, route; |
| 63 | device_t dev; |
| 64 | struct resource *res; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 65 | u8 *rcba; |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 66 | |
| 67 | dev = dev_find_slot(0, PCI_DEVFN(0x1F,0)); |
| 68 | res = find_resource(dev, RCBA); |
| 69 | if (!res) { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 70 | return NULL; |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 71 | } |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 72 | rcba = res2mmio(res, 0, 0); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 73 | |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 74 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 75 | |
Patrick Georgi | c8feedd | 2012-02-16 18:43:25 +0100 | [diff] [blame] | 76 | mptable_init(mc, LOCAL_APIC_ADDR); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 77 | |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 78 | smp_write_processors(mc); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 79 | |
| 80 | /* Get bus numbers */ |
| 81 | bus_chipset = 0; |
| 82 | |
| 83 | /* PCI */ |
| 84 | dev = dev_find_slot(0, PCI_DEVFN(0x1E,0)); |
| 85 | if (dev) { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 86 | bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 87 | } else { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 88 | printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); |
| 89 | bus_pci = 6; |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | dev = dev_find_slot(0, PCI_DEVFN(2,0)); |
| 93 | if(dev) { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 94 | bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 95 | } else { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 96 | printk(BIOS_DEBUG, "ERROR - could not find PCIe Port A 0:2.0, using defaults\n"); |
| 97 | bus_pcie_a = 1; |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | dev = dev_find_slot(0, PCI_DEVFN(3,0)); |
| 101 | if(dev) { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 102 | bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 103 | } else { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 104 | printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n"); |
| 105 | bus_pcie_a1 = 2; |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | dev = dev_find_slot(0, PCI_DEVFN(0x1C,0)); |
| 109 | if(dev) { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 110 | bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 111 | } else { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 112 | printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n"); |
| 113 | bus_pcie_b = 3; |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 114 | } |
| 115 | |
Patrick Georgi | 7411eab | 2010-11-22 14:14:56 +0000 | [diff] [blame] | 116 | mptable_write_buses(mc, NULL, &bus_isa); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 117 | |
| 118 | /*I/O APICs: APIC ID Version State Address*/ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 119 | smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR); |
Uwe Hermann | f9892166 | 2010-10-31 19:37:50 +0000 | [diff] [blame] | 120 | |
Patrick Georgi | c5b87c8 | 2010-05-20 15:28:19 +0000 | [diff] [blame] | 121 | mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 122 | |
| 123 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ |
Patrick Georgi | 6eb7a53 | 2011-10-07 21:42:52 +0200 | [diff] [blame] | 124 | mptable_lintsrc(mc, bus_isa); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 125 | |
| 126 | /* Internal PCI device for i3100 */ |
| 127 | |
| 128 | /* EDMA |
| 129 | */ |
| 130 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(1, INT_A), IO_APIC0, PIRQ_A); |
| 131 | |
| 132 | /* PCIe Port A |
| 133 | */ |
| 134 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(2, INT_A), IO_APIC0, PIRQ_A); |
| 135 | |
| 136 | /* PCIe Port A1 |
| 137 | */ |
| 138 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(3, INT_A), IO_APIC0, PIRQ_A); |
| 139 | |
| 140 | /* PCIe Port B |
| 141 | */ |
| 142 | for(i = 0; i < 4; i++) { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 143 | pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F; |
| 144 | if(pin > 0) { |
| 145 | pin -= 1; |
| 146 | route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07); |
| 147 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route); |
| 148 | } |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | /* USB 1.1 : device 29, function 0, 1 |
| 152 | */ |
| 153 | for(i = 0; i < 2; i++) { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 154 | pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F; |
| 155 | if(pin > 0) { |
| 156 | pin -= 1; |
| 157 | route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07); |
| 158 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route); |
| 159 | } |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 160 | } |
| 161 | |
| 162 | /* USB 2.0 : device 29, function 7 |
| 163 | */ |
Stefan Reinauer | 9fe4d79 | 2010-01-16 17:53:38 +0000 | [diff] [blame] | 164 | pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F; |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 165 | if(pin > 0) { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 166 | pin -= 1; |
| 167 | route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07); |
| 168 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 169 | } |
| 170 | |
| 171 | /* SATA : device 31 function 2 |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 172 | * SMBus : device 31 function 3 |
| 173 | * Performance counters : device 31 function 4 |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 174 | */ |
| 175 | for(i = 2; i < 5; i++) { |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 176 | pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F; |
| 177 | if(pin > 0) { |
| 178 | pin -= 1; |
| 179 | route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07); |
| 180 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route); |
| 181 | } |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | /* SLOTS */ |
| 185 | |
| 186 | /* PCIe 4x slot A |
| 187 | */ |
| 188 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A); |
| 189 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B); |
| 190 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C); |
| 191 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D); |
| 192 | |
| 193 | /* PCIe 4x slot A1 |
| 194 | */ |
| 195 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A); |
| 196 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B); |
| 197 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C); |
| 198 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D); |
| 199 | |
| 200 | /* PCIe 4x slot B |
| 201 | */ |
| 202 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A); |
| 203 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B); |
| 204 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C); |
| 205 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D); |
| 206 | |
| 207 | /* PCI slot |
| 208 | */ |
| 209 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A); |
| 210 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B); |
| 211 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C); |
| 212 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D); |
| 213 | |
| 214 | /* There is no extension information... */ |
| 215 | |
| 216 | /* Compute the checksums */ |
Patrick Georgi | b0a9c5c | 2011-10-07 23:01:55 +0200 | [diff] [blame] | 217 | return mptable_finalize(mc); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | unsigned long write_smp_table(unsigned long addr) |
| 221 | { |
| 222 | void *v; |
Patrick Georgi | c75c79b | 2011-10-07 22:41:07 +0200 | [diff] [blame] | 223 | v = smp_write_floating_table(addr, 0); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 224 | return (unsigned long)smp_write_config_table(v); |
| 225 | } |