Add support for the Intel Eagle Heights development board.
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
new file mode 100644
index 0000000..7f2ca35
--- /dev/null
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -0,0 +1,323 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+// Generate MP-table IRQ numbers for PCI devices.
+#define IO_APIC0 2
+
+#define INT_A 0
+#define INT_B 1
+#define INT_C 2
+#define INT_D 3
+#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)
+
+#define PIRQ_A 16
+#define PIRQ_B 17
+#define PIRQ_C 18
+#define PIRQ_D 19
+#define PIRQ_E 20
+#define PIRQ_F 21
+#define PIRQ_G 22
+#define PIRQ_H 23
+
+// RCBA
+#define RCBA 0xF0
+
+#define RCBA_D31IP 0x3100
+#define RCBA_D30IP 0x3104
+#define RCBA_D29IP 0x3108
+#define RCBA_D28IP 0x310C
+#define RCBA_D31IR 0x3140
+#define RCBA_D30IR 0x3142
+#define RCBA_D29IR 0x3144
+#define RCBA_D28IR 0x3146
+
+void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "Intel ";
+ static const char productid[12] = "EagleHeights";
+ struct mp_config_table *mc;
+ unsigned char bus_num, bus_chipset, bus_isa, bus_pci;
+ unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
+ int i;
+ uint32_t pin, route;
+ device_t dev;
+ struct resource *res;
+ unsigned long rcba;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
+ res = find_resource(dev, RCBA);
+ if (!res) {
+ return;
+ }
+ rcba = res->base;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+ /* Get bus numbers */
+ bus_chipset = 0;
+
+ /* PCI */
+ dev = dev_find_slot(0, PCI_DEVFN(0x1E,0));
+ if (dev) {
+ bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ } else {
+ printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+ bus_pci = 6;
+ bus_isa = 7;
+ }
+
+ dev = dev_find_slot(0, PCI_DEVFN(2,0));
+ if(dev) {
+ bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk_debug("ERROR - could not find PCIe Port A 0:2.0, using defaults\n");
+ bus_pcie_a = 1;
+ }
+
+ dev = dev_find_slot(0, PCI_DEVFN(3,0));
+ if(dev) {
+ bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+ bus_pcie_a1 = 2;
+ }
+
+ dev = dev_find_slot(0, PCI_DEVFN(0x1C,0));
+ if(dev) {
+ bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+ bus_pcie_b = 3;
+ }
+
+ /*Bus: Bus ID Type*/
+ for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+ smp_write_bus(mc, bus_num, "PCI ");
+ }
+ smp_write_bus(mc, bus_isa, "ISA ");
+
+ /*I/O APICs: APIC ID Version State Address*/
+ smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ /*
+ {
+ device_t dev;
+ struct resource *res;
+ dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 3, 0x20, res->base);
+ }
+ }
+ dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 4, 0x20, res->base);
+ }
+ }
+ dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 5, 0x20, res->base);
+ }
+ }
+ dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 8, 0x20, res->base);
+ }
+ }
+ }
+ */
+ /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ /* IRQ0 8254 Counter 0, MNT0 */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, IO_APIC0, 0);
+ /* IRQ1 Keyboard */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 1, IO_APIC0, 1);
+ /* IRQ2 8259 cascade only */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, IO_APIC0, 2);
+ /* IRQ3 COM2, Option for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 3, IO_APIC0, 3);
+ /* IRQ4 COM1, Option for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 4, IO_APIC0, 4);
+ /* IRQ5 Option for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 5, IO_APIC0, 5);
+ /* IRQ6 Option for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 6, IO_APIC0, 6);
+ /* IRQ7 OPtion for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 7, IO_APIC0, 7);
+ /* IRQ8# RTC, MNT1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, bus_isa, 8, IO_APIC0, 8);
+ /* IRQ9 Option for PIRQx, SCI, TCO */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 9, IO_APIC0, 9);
+ /* IRQ10 Option for PIRQx, SCI, TCO */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 10);
+ /* IRQ11 Option for PIRQx, SCI, TCO, MMT2 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 11);
+ /* IRQ12 Mouse, Option for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 12);
+ /* IRQ13 Floating point interrupt generated off of the processor assertion of FERR# */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 13, IO_APIC0, 13);
+ /* IRQ14 PIRQx Sata primary (legacy mode) */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 14, IO_APIC0, 14);
+ /* IRQ15 PIRQx Sata secondary (legacy mode) */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 15, IO_APIC0, 15);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0);
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1);
+
+ /* Internal PCI device for i3100 */
+
+ /* EDMA
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(1, INT_A), IO_APIC0, PIRQ_A);
+
+ /* PCIe Port A
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(2, INT_A), IO_APIC0, PIRQ_A);
+
+ /* PCIe Port A1
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(3, INT_A), IO_APIC0, PIRQ_A);
+
+ /* PCIe Port B
+ */
+ for(i = 0; i < 4; i++) {
+ pin = (readl(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
+ if(pin > 0) {
+ pin -= 1;
+ route = PIRQ_A + ((readw(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
+ }
+ }
+
+ /* USB 1.1 : device 29, function 0, 1
+ */
+ for(i = 0; i < 2; i++) {
+ pin = (readl(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
+ if(pin > 0) {
+ pin -= 1;
+ route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
+ }
+ }
+
+ /* USB 2.0 : device 29, function 7
+ */
+ pin = (readl(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
+ if(pin > 0) {
+ pin -= 1;
+ route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
+ }
+
+ /* SATA : device 31 function 2
+ SMBus : device 31 function 3
+ Performance counters : device 31 function 4
+ */
+ for(i = 2; i < 5; i++) {
+ pin = (readl(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
+ if(pin > 0) {
+ pin -= 1;
+ route = PIRQ_A + ((readw(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
+ }
+ }
+
+ /* SLOTS */
+
+ /* PCIe 4x slot A
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+ /* PCIe 4x slot A1
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+ /* PCIe 4x slot B
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+ /* PCI slot
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk_debug("Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}