blob: a9cfb495273946dcd970c2acde36c8add82ddbad [file] [log] [blame]
Aaron Durbinf6933a62012-10-30 09:09:39 -05001chip northbridge/intel/haswell
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01002 # IGD Displays
3 register "gfx.ndid" = "3"
4 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
Aaron Durbinf6933a62012-10-30 09:09:39 -05005
6 # Enable DisplayPort 1 Hotplug with 6ms pulse
7 register "gpu_dp_d_hotplug" = "0x06"
8
9 # Enable DisplayPort 0 Hotplug with 6ms pulse
10 register "gpu_dp_c_hotplug" = "0x06"
11
12 # Enable DVI Hotplug with 6ms pulse
13 register "gpu_dp_b_hotplug" = "0x06"
14
15 device cpu_cluster 0 on
Aaron Durbinf6933a62012-10-30 09:09:39 -050016 chip cpu/intel/haswell
Matt DeVillier31769d92015-04-30 01:19:16 -050017 device lapic 0 on end
Aaron Durbinf6933a62012-10-30 09:09:39 -050018 # Magic APIC ID to locate this chip
19 device lapic 0xACAC off end
20
Aaron Durbin7c351312013-04-10 14:46:25 -050021 register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
22 register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
23 register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
Aaron Durbinf6933a62012-10-30 09:09:39 -050024
Aaron Durbin7c351312013-04-10 14:46:25 -050025 register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
26 register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
27 register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
Aaron Durbinf6933a62012-10-30 09:09:39 -050028 end
29 end
30
31 device domain 0 on
32 device pci 00.0 on end # host bridge
33 device pci 02.0 on end # vga controller
34
35 chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
36 register "pirqa_routing" = "0x8b"
37 register "pirqb_routing" = "0x8a"
38 register "pirqc_routing" = "0x8b"
39 register "pirqd_routing" = "0x8b"
40 register "pirqe_routing" = "0x80"
41 register "pirqf_routing" = "0x80"
42 register "pirqg_routing" = "0x80"
43 register "pirqh_routing" = "0x80"
44
45 # GPI routing
46 # 0 No effect (default)
47 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
48 # 2 SCI (if corresponding GPIO_EN bit is also set)
49 register "gpi1_routing" = "1"
50 register "gpi14_routing" = "2"
Aaron Durbinef8f4c72012-12-12 12:32:43 -060051 register "alt_gp_smi_en" = "0x0000"
Duncan Laurie467f31d2013-03-08 17:00:37 -080052 register "gpe0_en_1" = "0x4000"
Aaron Durbinf6933a62012-10-30 09:09:39 -050053
54 register "ide_legacy_combined" = "0x0"
55 register "sata_ahci" = "0x1"
56 register "sata_port_map" = "0x3f"
57
58 # SuperIO range is 0x700-0x73f
59 register "gen2_dec" = "0x003c0701"
60
61 device pci 16.0 on end # Management Engine Interface 1
62 device pci 16.1 off end # Management Engine Interface 2
63 device pci 16.2 off end # Management Engine IDE-R
64 device pci 16.3 off end # Management Engine KT
65 device pci 19.0 off end # Intel Gigabit Ethernet
66 device pci 1a.0 on end # USB2 EHCI #2
67 device pci 1b.0 on end # High Definition Audio
68 device pci 1c.0 on end # PCIe Port #1 (WLAN)
69 device pci 1c.1 off end # PCIe Port #2
70 device pci 1c.2 on end # PCIe Port #3 (Debug)
71 device pci 1c.3 on end # PCIe Port #4 (LAN)
72 device pci 1c.4 off end # PCIe Port #5
73 device pci 1c.5 off end # PCIe Port #6
74 device pci 1c.6 off end # PCIe Port #7
75 device pci 1c.7 off end # PCIe Port #8
76 device pci 1d.0 on end # USB2 EHCI #1
77 device pci 1e.0 off end # PCI bridge
78 device pci 1f.0 on end # LPC bridge
79 device pci 1f.2 on end # SATA Controller 1
80 device pci 1f.3 on end # SMBus
81 device pci 1f.5 off end # SATA Controller 2
82 device pci 1f.6 on end # Thermal
83 end
84 end
85end