| Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame^] | 1 | chip northbridge/intel/haswell |
| 2 | |
| 3 | # Enable DisplayPort 1 Hotplug with 6ms pulse |
| 4 | register "gpu_dp_d_hotplug" = "0x06" |
| 5 | |
| 6 | # Enable DisplayPort 0 Hotplug with 6ms pulse |
| 7 | register "gpu_dp_c_hotplug" = "0x06" |
| 8 | |
| 9 | # Enable DVI Hotplug with 6ms pulse |
| 10 | register "gpu_dp_b_hotplug" = "0x06" |
| 11 | |
| 12 | device cpu_cluster 0 on |
| 13 | chip cpu/intel/socket_rPGA989 |
| 14 | device lapic 0 on end |
| 15 | end |
| 16 | chip cpu/intel/haswell |
| 17 | # Magic APIC ID to locate this chip |
| 18 | device lapic 0xACAC off end |
| 19 | |
| 20 | register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) |
| 21 | register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) |
| 22 | register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) |
| 23 | |
| 24 | register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) |
| 25 | register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) |
| 26 | register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) |
| 27 | end |
| 28 | end |
| 29 | |
| 30 | device domain 0 on |
| 31 | device pci 00.0 on end # host bridge |
| 32 | device pci 02.0 on end # vga controller |
| 33 | |
| 34 | chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH |
| 35 | register "pirqa_routing" = "0x8b" |
| 36 | register "pirqb_routing" = "0x8a" |
| 37 | register "pirqc_routing" = "0x8b" |
| 38 | register "pirqd_routing" = "0x8b" |
| 39 | register "pirqe_routing" = "0x80" |
| 40 | register "pirqf_routing" = "0x80" |
| 41 | register "pirqg_routing" = "0x80" |
| 42 | register "pirqh_routing" = "0x80" |
| 43 | |
| 44 | # GPI routing |
| 45 | # 0 No effect (default) |
| 46 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 47 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 48 | register "gpi1_routing" = "1" |
| 49 | register "gpi14_routing" = "2" |
| 50 | register "alt_gp_smi_en" = "0x0002" |
| 51 | register "gpe0_en" = "0x4000" |
| 52 | |
| 53 | register "ide_legacy_combined" = "0x0" |
| 54 | register "sata_ahci" = "0x1" |
| 55 | register "sata_port_map" = "0x3f" |
| 56 | |
| 57 | # SuperIO range is 0x700-0x73f |
| 58 | register "gen2_dec" = "0x003c0701" |
| 59 | |
| 60 | device pci 16.0 on end # Management Engine Interface 1 |
| 61 | device pci 16.1 off end # Management Engine Interface 2 |
| 62 | device pci 16.2 off end # Management Engine IDE-R |
| 63 | device pci 16.3 off end # Management Engine KT |
| 64 | device pci 19.0 off end # Intel Gigabit Ethernet |
| 65 | device pci 1a.0 on end # USB2 EHCI #2 |
| 66 | device pci 1b.0 on end # High Definition Audio |
| 67 | device pci 1c.0 on end # PCIe Port #1 (WLAN) |
| 68 | device pci 1c.1 off end # PCIe Port #2 |
| 69 | device pci 1c.2 on end # PCIe Port #3 (Debug) |
| 70 | device pci 1c.3 on end # PCIe Port #4 (LAN) |
| 71 | device pci 1c.4 off end # PCIe Port #5 |
| 72 | device pci 1c.5 off end # PCIe Port #6 |
| 73 | device pci 1c.6 off end # PCIe Port #7 |
| 74 | device pci 1c.7 off end # PCIe Port #8 |
| 75 | device pci 1d.0 on end # USB2 EHCI #1 |
| 76 | device pci 1e.0 off end # PCI bridge |
| 77 | device pci 1f.0 on end # LPC bridge |
| 78 | device pci 1f.2 on end # SATA Controller 1 |
| 79 | device pci 1f.3 on end # SMBus |
| 80 | device pci 1f.5 off end # SATA Controller 2 |
| 81 | device pci 1f.6 on end # Thermal |
| 82 | end |
| 83 | end |
| 84 | end |