blob: 3e841e03ab7336b8c435a8574a2043e347f4ff73 [file] [log] [blame]
Aaron Durbinf6933a62012-10-30 09:09:39 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Aaron Durbinf6933a62012-10-30 09:09:39 -050014 */
15
16/* This is board specific information: IRQ routing for IvyBridge */
17
18// PCI Interrupt Routing
19Method(_PRT)
20{
21 If (PICM) {
22 Return (Package() {
23 // Onboard graphics (IGD) 0:2.0
24 Package() { 0x0002ffff, 0, 0, 16 },
25 // High Definition Audio 0:1b.0
26 Package() { 0x001bffff, 0, 0, 22 },
27 // PCIe Root Ports 0:1c.x
28 Package() { 0x001cffff, 0, 0, 17 },
29 Package() { 0x001cffff, 1, 0, 18 },
30 Package() { 0x001cffff, 2, 0, 19 },
31 Package() { 0x001cffff, 3, 0, 20 },
32 // EHCI #1 0:1d.0
33 Package() { 0x001dffff, 0, 0, 19 },
34 // EHCI #2 0:1a.0
35 Package() { 0x001affff, 0, 0, 20 },
36 // LPC devices 0:1f.0
37 Package() { 0x001fffff, 0, 0, 21 },
38 Package() { 0x001fffff, 1, 0, 22 },
39 Package() { 0x001fffff, 2, 0, 23 },
40 Package() { 0x001fffff, 3, 0, 16 },
41 })
42 } Else {
43 Return (Package() {
44 // Onboard graphics (IGD) 0:2.0
45 Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
46 // High Definition Audio 0:1b.0
47 Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
48 // PCIe Root Ports 0:1c.x
49 Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
50 Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
51 Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
52 Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
53 // EHCI #1 0:1d.0
54 Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
55 // EHCI #2 0:1a.0
56 Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
57 // LPC device 0:1f.0
58 Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
59 Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
60 Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
61 Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
62 })
63 }
64}