| Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | /* This is board specific information: IRQ routing for IvyBridge */ |
| 21 | |
| 22 | // PCI Interrupt Routing |
| 23 | Method(_PRT) |
| 24 | { |
| 25 | If (PICM) { |
| 26 | Return (Package() { |
| 27 | // Onboard graphics (IGD) 0:2.0 |
| 28 | Package() { 0x0002ffff, 0, 0, 16 }, |
| 29 | // High Definition Audio 0:1b.0 |
| 30 | Package() { 0x001bffff, 0, 0, 22 }, |
| 31 | // PCIe Root Ports 0:1c.x |
| 32 | Package() { 0x001cffff, 0, 0, 17 }, |
| 33 | Package() { 0x001cffff, 1, 0, 18 }, |
| 34 | Package() { 0x001cffff, 2, 0, 19 }, |
| 35 | Package() { 0x001cffff, 3, 0, 20 }, |
| 36 | // EHCI #1 0:1d.0 |
| 37 | Package() { 0x001dffff, 0, 0, 19 }, |
| 38 | // EHCI #2 0:1a.0 |
| 39 | Package() { 0x001affff, 0, 0, 20 }, |
| 40 | // LPC devices 0:1f.0 |
| 41 | Package() { 0x001fffff, 0, 0, 21 }, |
| 42 | Package() { 0x001fffff, 1, 0, 22 }, |
| 43 | Package() { 0x001fffff, 2, 0, 23 }, |
| 44 | Package() { 0x001fffff, 3, 0, 16 }, |
| 45 | }) |
| 46 | } Else { |
| 47 | Return (Package() { |
| 48 | // Onboard graphics (IGD) 0:2.0 |
| 49 | Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, |
| 50 | // High Definition Audio 0:1b.0 |
| 51 | Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, |
| 52 | // PCIe Root Ports 0:1c.x |
| 53 | Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, |
| 54 | Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, |
| 55 | Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, |
| 56 | Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, |
| 57 | // EHCI #1 0:1d.0 |
| 58 | Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, |
| 59 | // EHCI #2 0:1a.0 |
| 60 | Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, |
| 61 | // LPC device 0:1f.0 |
| 62 | Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, |
| 63 | Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, |
| 64 | Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, |
| 65 | Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, |
| 66 | }) |
| 67 | } |
| 68 | } |
| 69 | |