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Ricardo Martins892d8d22012-08-06 05:40:07 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ricardo Martins892d8d22012-08-06 05:40:07 +010015 */
16
17#include <device/pci_ids.h>
18#include <arch/pirq_routing.h>
19
20/* Platform IRQs */
21#define PIRQA 10
22#define PIRQB 10
23#define PIRQC 11
24#define PIRQD 11
25
26/* Links */
27#define L_PIRQN 0
28#define L_PIRQA 1
29#define L_PIRQB 2
30#define L_PIRQC 3
31#define L_PIRQD 4
32
33/* Bitmaps */
34#define B_LINKN (0)
35#define B_LINK0 (1 << PIRQA)
36#define B_LINK1 (1 << PIRQB)
37#define B_LINK2 (1 << PIRQC)
38#define B_LINK3 (1 << PIRQD)
39
Stefan Reinauera47bd912012-11-15 15:15:15 -080040static const struct irq_routing_table intel_irq_routing_table = {
Ricardo Martins892d8d22012-08-06 05:40:07 +010041 PIRQ_SIGNATURE, /* u32 signature */
42 PIRQ_VERSION, /* u16 version */
43 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
44 0x00, /* Interrupt router bus */
45 (0x0f << 3) | 0x0, /* Interrupt router dev */
46 (B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */
47 PCI_VENDOR_ID_AMD, /* Vendor */
48 PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */
49 0, /* Miniport */
50 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
51 0x27, /* Checksum */
52 {
53 [0] = { /* Host bridge */
54 .slot = 0x00,
55 .bus = 0x00,
56 .devfn = (0x01 << 3) | 0x0,
57 .irq = {
58 [0] = {
59 .link = L_PIRQA,
60 .bitmap = B_LINK0
61 },
62 [1] = {
63 .link = L_PIRQN,
64 .bitmap = B_LINKN
65 },
66 [2] = {
67 .link = L_PIRQN,
68 .bitmap = B_LINKN
69 },
70 [3] = {
71 .link = L_PIRQN,
72 .bitmap = B_LINKN
73 }
74 }
75 },
76
77 [1] = { /* ISA bridge */
78 .slot = 0x00,
79 .bus = 0x00,
80 .devfn = (0x0f << 3) | 0x0,
81 .irq = {
82 [0] = {
83 .link = L_PIRQN,
84 .bitmap = B_LINKN
85 },
86 [1] = {
87 .link = L_PIRQB,
88 .bitmap = B_LINK1
89 },
90 [2] = {
91 .link = L_PIRQN,
92 .bitmap = B_LINKN
93 },
94 [3] = {
95 .link = L_PIRQD,
96 .bitmap = B_LINK3
97 }
98 }
99 },
100
101 [2] = { /* Ethernet */
102 .slot = 0x00,
103 .bus = 0x00,
104 .devfn = (0x0e << 3) | 0x0,
105 .irq = {
106 [0] = {
107 .link = L_PIRQD,
108 .bitmap = B_LINK3
109 },
110 [1] = {
111 .link = L_PIRQN,
112 .bitmap = B_LINKN
113 },
114 [2] = {
115 .link = L_PIRQN,
116 .bitmap = B_LINKN
117 },
118 [3] = {
119 .link = L_PIRQN,
120 .bitmap = B_LINKN
121 }
122 }
123 }
124 }
125};
126
127unsigned long write_pirq_routing_table(unsigned long addr)
128{
Stefan Reinauera47bd912012-11-15 15:15:15 -0800129 return copy_pirq_routing_table(addr, &intel_irq_routing_table);
Ricardo Martins892d8d22012-08-06 05:40:07 +0100130}