Ricardo Martins | 892d8d2 | 2012-08-06 05:40:07 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <arch/pirq_routing.h> |
| 23 | |
| 24 | /* Platform IRQs */ |
| 25 | #define PIRQA 10 |
| 26 | #define PIRQB 10 |
| 27 | #define PIRQC 11 |
| 28 | #define PIRQD 11 |
| 29 | |
| 30 | /* Links */ |
| 31 | #define L_PIRQN 0 |
| 32 | #define L_PIRQA 1 |
| 33 | #define L_PIRQB 2 |
| 34 | #define L_PIRQC 3 |
| 35 | #define L_PIRQD 4 |
| 36 | |
| 37 | /* Bitmaps */ |
| 38 | #define B_LINKN (0) |
| 39 | #define B_LINK0 (1 << PIRQA) |
| 40 | #define B_LINK1 (1 << PIRQB) |
| 41 | #define B_LINK2 (1 << PIRQC) |
| 42 | #define B_LINK3 (1 << PIRQD) |
| 43 | |
| 44 | const struct irq_routing_table intel_irq_routing_table = { |
| 45 | PIRQ_SIGNATURE, /* u32 signature */ |
| 46 | PIRQ_VERSION, /* u16 version */ |
| 47 | 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ |
| 48 | 0x00, /* Interrupt router bus */ |
| 49 | (0x0f << 3) | 0x0, /* Interrupt router dev */ |
| 50 | (B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */ |
| 51 | PCI_VENDOR_ID_AMD, /* Vendor */ |
| 52 | PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */ |
| 53 | 0, /* Miniport */ |
| 54 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
| 55 | 0x27, /* Checksum */ |
| 56 | { |
| 57 | [0] = { /* Host bridge */ |
| 58 | .slot = 0x00, |
| 59 | .bus = 0x00, |
| 60 | .devfn = (0x01 << 3) | 0x0, |
| 61 | .irq = { |
| 62 | [0] = { |
| 63 | .link = L_PIRQA, |
| 64 | .bitmap = B_LINK0 |
| 65 | }, |
| 66 | [1] = { |
| 67 | .link = L_PIRQN, |
| 68 | .bitmap = B_LINKN |
| 69 | }, |
| 70 | [2] = { |
| 71 | .link = L_PIRQN, |
| 72 | .bitmap = B_LINKN |
| 73 | }, |
| 74 | [3] = { |
| 75 | .link = L_PIRQN, |
| 76 | .bitmap = B_LINKN |
| 77 | } |
| 78 | } |
| 79 | }, |
| 80 | |
| 81 | [1] = { /* ISA bridge */ |
| 82 | .slot = 0x00, |
| 83 | .bus = 0x00, |
| 84 | .devfn = (0x0f << 3) | 0x0, |
| 85 | .irq = { |
| 86 | [0] = { |
| 87 | .link = L_PIRQN, |
| 88 | .bitmap = B_LINKN |
| 89 | }, |
| 90 | [1] = { |
| 91 | .link = L_PIRQB, |
| 92 | .bitmap = B_LINK1 |
| 93 | }, |
| 94 | [2] = { |
| 95 | .link = L_PIRQN, |
| 96 | .bitmap = B_LINKN |
| 97 | }, |
| 98 | [3] = { |
| 99 | .link = L_PIRQD, |
| 100 | .bitmap = B_LINK3 |
| 101 | } |
| 102 | } |
| 103 | }, |
| 104 | |
| 105 | [2] = { /* Ethernet */ |
| 106 | .slot = 0x00, |
| 107 | .bus = 0x00, |
| 108 | .devfn = (0x0e << 3) | 0x0, |
| 109 | .irq = { |
| 110 | [0] = { |
| 111 | .link = L_PIRQD, |
| 112 | .bitmap = B_LINK3 |
| 113 | }, |
| 114 | [1] = { |
| 115 | .link = L_PIRQN, |
| 116 | .bitmap = B_LINKN |
| 117 | }, |
| 118 | [2] = { |
| 119 | .link = L_PIRQN, |
| 120 | .bitmap = B_LINKN |
| 121 | }, |
| 122 | [3] = { |
| 123 | .link = L_PIRQN, |
| 124 | .bitmap = B_LINKN |
| 125 | } |
| 126 | } |
| 127 | } |
| 128 | } |
| 129 | }; |
| 130 | |
| 131 | unsigned long write_pirq_routing_table(unsigned long addr) |
| 132 | { |
| 133 | return copy_pirq_routing_table(addr); |
| 134 | } |