blob: 3aa02d8deb3b77eb7901531ee253e7fa556b9657 [file] [log] [blame]
Michael Tasche446c5dc2015-12-03 17:07:01 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC.
6 * Copyright (C) 2014 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
Ben Gardnerfa6014a2015-12-08 21:20:25 -060018#include <soc/romstage.h>
Michael Tasche446c5dc2015-12-03 17:07:01 +010019#include <drivers/intel/fsp1_0/fsp_util.h>
20#include <pc80/mc146818rtc.h>
21#include <console/console.h>
Ben Gardnerfa6014a2015-12-08 21:20:25 -060022#include <soc/gpio.h>
23#include <soc/intel/fsp_baytrail/chip.h>
Michael Tasche446c5dc2015-12-03 17:07:01 +010024
25/**
26 * /brief mainboard call for setup that needs to be done before fsp init
27 *
28 */
29void early_mainboard_romstage_entry()
30{
31
32}
33
34/**
35 * Get function disables - most of these will be done automatically
36 * @param fd_mask
37 * @param fd2_mask
38 */
39void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
40{
41
42}
43
44/**
45 * /brief mainboard call for setup that needs to be done after fsp init
46 *
47 */
48void late_mainboard_romstage_entry()
49{
50
51 configure_ssus_gpio(27, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
52 configure_ssus_gpio(28, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
53 configure_ssus_gpio(29, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
54 configure_ssus_gpio(30, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
55
56 printk(0, "SW450: %d %d %d %d\n",
57 read_ssus_gpio(27),
58 read_ssus_gpio(28),
59 read_ssus_gpio(29),
60 read_ssus_gpio(30) );
61
62}
63
64void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
65{
66 UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
67 u8 use_xhci = UpdData->PcdEnableXhci;
68
69 /* Update XHCI UPD value if required */
70 get_option(&use_xhci, "use_xhci_over_ehci");
71 if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
72 UpdData->PcdEnableXhci = use_xhci;
73 printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",
74 UpdData->PcdEnableXhci?"Enabled":"Disabled");
75 }
76
77 return;
78}