blob: 0bea8970e938bb27811327bc1267b88afdcd4edb [file] [log] [blame]
Yuichi Itob31c3d12016-07-28 13:34:18 +09001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
17#define _PLATFORM_GNB_PCIE_COMPLEX_H
18
Yuichi Itoc4ddfe42016-07-28 13:34:18 +090019/*
20 * GNB GPP Port4
21 * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable
22 * GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
23 * GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
24 * GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
25 * 2:Half-swing(0db) 3:Half-swing(-3.5db)
26 * 4:extended length(-6db) 5:extended length(-8db)
27 * GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
28 */
29#define GNB_GPP_PORT4_PORT_PRESENT 1
30#define GNB_GPP_PORT4_SPEED_MODE 2
31#define GNB_GPP_PORT4_LINK_ASPM 3
32#define GNB_GPP_PORT4_CHANNEL_TYPE 4
33#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0
Yuichi Itob31c3d12016-07-28 13:34:18 +090034
Yuichi Itoc4ddfe42016-07-28 13:34:18 +090035/*
36 * GNB GPP Port5
37 * GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable
38 * GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
39 * GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
40 * GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
41 * 2:Half-swing(0db) 3:Half-swing(-3.5db)
42 * 4:extended length(-6db) 5:extended length(-8db)
43 * GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
44 */
45#define GNB_GPP_PORT5_PORT_PRESENT 0
46#define GNB_GPP_PORT5_SPEED_MODE 2
47#define GNB_GPP_PORT5_LINK_ASPM 3
48#define GNB_GPP_PORT5_CHANNEL_TYPE 4
49#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0
Yuichi Itob31c3d12016-07-28 13:34:18 +090050
Yuichi Itoc4ddfe42016-07-28 13:34:18 +090051/*
52 * GNB GPP Port6
53 * GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable
54 * GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
55 * GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
56 * GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
57 * 2:Half-swing(0db) 3:Half-swing(-3.5db)
58 * 4:extended length(-6db) 5:extended length(-8db)
59 * GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
60 */
61#define GNB_GPP_PORT6_PORT_PRESENT 0
62#define GNB_GPP_PORT6_SPEED_MODE 2
63#define GNB_GPP_PORT6_LINK_ASPM 3
64#define GNB_GPP_PORT6_CHANNEL_TYPE 4
65#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0
Yuichi Itob31c3d12016-07-28 13:34:18 +090066
Yuichi Itoc4ddfe42016-07-28 13:34:18 +090067/*
68 * GNB GPP Port7
69 * GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable
70 * GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
71 * GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
72 * GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
73 * 2:Half-swing(0db) 3:Half-swing(-3.5db)
74 * 4:extended length(-6db) 5:extended length(-8db)
75 * GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
76 */
77#define GNB_GPP_PORT7_PORT_PRESENT 0
78#define GNB_GPP_PORT7_SPEED_MODE 2
79#define GNB_GPP_PORT7_LINK_ASPM 3
80#define GNB_GPP_PORT7_CHANNEL_TYPE 4
81#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0
Yuichi Itob31c3d12016-07-28 13:34:18 +090082
Yuichi Itoc4ddfe42016-07-28 13:34:18 +090083/*
84 * GNB GPP Port8
85 * GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable
86 * GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2
87 * GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1
88 * GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db)
89 * 2:Half-swing(0db) 3:Half-swing(-3.5db)
90 * 4:extended length(-6db) 5:extended length(-8db)
91 * GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced
92 */
93#define GNB_GPP_PORT8_PORT_PRESENT 1
94#define GNB_GPP_PORT8_SPEED_MODE 2
95#define GNB_GPP_PORT8_LINK_ASPM 3
96#define GNB_GPP_PORT8_CHANNEL_TYPE 4
97#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0
Yuichi Itob31c3d12016-07-28 13:34:18 +090098
99
100#endif //_PLATFORM_GNB_PCIE_COMPLEX_H