| Yuichi Ito | b31c3d1 | 2016-07-28 13:34:18 +0900 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H |
| 17 | #define _PLATFORM_GNB_PCIE_COMPLEX_H |
| 18 | |
| 19 | #include "Porting.h" |
| 20 | #include "AGESA.h" |
| 21 | #include "amdlib.h" |
| 22 | #include <cpu/amd/agesa/s3_resume.h> |
| 23 | |
| Yuichi Ito | c4ddfe4 | 2016-07-28 13:34:18 +0900 | [diff] [blame^] | 24 | /* |
| 25 | * GNB GPP Port4 |
| 26 | * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable |
| 27 | * GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 |
| 28 | * GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 |
| 29 | * GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) |
| 30 | * 2:Half-swing(0db) 3:Half-swing(-3.5db) |
| 31 | * 4:extended length(-6db) 5:extended length(-8db) |
| 32 | * GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced |
| 33 | */ |
| 34 | #define GNB_GPP_PORT4_PORT_PRESENT 1 |
| 35 | #define GNB_GPP_PORT4_SPEED_MODE 2 |
| 36 | #define GNB_GPP_PORT4_LINK_ASPM 3 |
| 37 | #define GNB_GPP_PORT4_CHANNEL_TYPE 4 |
| 38 | #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 |
| Yuichi Ito | b31c3d1 | 2016-07-28 13:34:18 +0900 | [diff] [blame] | 39 | |
| Yuichi Ito | c4ddfe4 | 2016-07-28 13:34:18 +0900 | [diff] [blame^] | 40 | /* |
| 41 | * GNB GPP Port5 |
| 42 | * GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable |
| 43 | * GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 |
| 44 | * GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 |
| 45 | * GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) |
| 46 | * 2:Half-swing(0db) 3:Half-swing(-3.5db) |
| 47 | * 4:extended length(-6db) 5:extended length(-8db) |
| 48 | * GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced |
| 49 | */ |
| 50 | #define GNB_GPP_PORT5_PORT_PRESENT 0 |
| 51 | #define GNB_GPP_PORT5_SPEED_MODE 2 |
| 52 | #define GNB_GPP_PORT5_LINK_ASPM 3 |
| 53 | #define GNB_GPP_PORT5_CHANNEL_TYPE 4 |
| 54 | #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 |
| Yuichi Ito | b31c3d1 | 2016-07-28 13:34:18 +0900 | [diff] [blame] | 55 | |
| Yuichi Ito | c4ddfe4 | 2016-07-28 13:34:18 +0900 | [diff] [blame^] | 56 | /* |
| 57 | * GNB GPP Port6 |
| 58 | * GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable |
| 59 | * GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 |
| 60 | * GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 |
| 61 | * GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) |
| 62 | * 2:Half-swing(0db) 3:Half-swing(-3.5db) |
| 63 | * 4:extended length(-6db) 5:extended length(-8db) |
| 64 | * GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced |
| 65 | */ |
| 66 | #define GNB_GPP_PORT6_PORT_PRESENT 0 |
| 67 | #define GNB_GPP_PORT6_SPEED_MODE 2 |
| 68 | #define GNB_GPP_PORT6_LINK_ASPM 3 |
| 69 | #define GNB_GPP_PORT6_CHANNEL_TYPE 4 |
| 70 | #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 |
| Yuichi Ito | b31c3d1 | 2016-07-28 13:34:18 +0900 | [diff] [blame] | 71 | |
| Yuichi Ito | c4ddfe4 | 2016-07-28 13:34:18 +0900 | [diff] [blame^] | 72 | /* |
| 73 | * GNB GPP Port7 |
| 74 | * GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable |
| 75 | * GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 |
| 76 | * GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 |
| 77 | * GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) |
| 78 | * 2:Half-swing(0db) 3:Half-swing(-3.5db) |
| 79 | * 4:extended length(-6db) 5:extended length(-8db) |
| 80 | * GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced |
| 81 | */ |
| 82 | #define GNB_GPP_PORT7_PORT_PRESENT 0 |
| 83 | #define GNB_GPP_PORT7_SPEED_MODE 2 |
| 84 | #define GNB_GPP_PORT7_LINK_ASPM 3 |
| 85 | #define GNB_GPP_PORT7_CHANNEL_TYPE 4 |
| 86 | #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 |
| Yuichi Ito | b31c3d1 | 2016-07-28 13:34:18 +0900 | [diff] [blame] | 87 | |
| Yuichi Ito | c4ddfe4 | 2016-07-28 13:34:18 +0900 | [diff] [blame^] | 88 | /* |
| 89 | * GNB GPP Port8 |
| 90 | * GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable |
| 91 | * GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 |
| 92 | * GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 |
| 93 | * GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) |
| 94 | * 2:Half-swing(0db) 3:Half-swing(-3.5db) |
| 95 | * 4:extended length(-6db) 5:extended length(-8db) |
| 96 | * GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced |
| 97 | */ |
| 98 | #define GNB_GPP_PORT8_PORT_PRESENT 1 |
| 99 | #define GNB_GPP_PORT8_SPEED_MODE 2 |
| 100 | #define GNB_GPP_PORT8_LINK_ASPM 3 |
| 101 | #define GNB_GPP_PORT8_CHANNEL_TYPE 4 |
| 102 | #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 |
| Yuichi Ito | b31c3d1 | 2016-07-28 13:34:18 +0900 | [diff] [blame] | 103 | |
| 104 | |
| 105 | #endif //_PLATFORM_GNB_PCIE_COMPLEX_H |