blob: 3388322aa50c24c2ec834cb8392171739d084f2e [file] [log] [blame]
Noah Glovskycc93ce72016-04-19 15:43:17 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
Vladimir Serbinenko55f3e2f2015-05-29 22:07:29 +020014#include <stdint.h>
15#include <string.h>
16#include <lib.h>
17#include <timestamp.h>
18#include <arch/byteorder.h>
19#include <arch/io.h>
20#include <device/pci_def.h>
21#include <device/pnp_def.h>
22#include <cpu/x86/lapic.h>
23#include <arch/acpi.h>
24#include <console/console.h>
25#include "northbridge/intel/sandybridge/sandybridge.h"
26#include "northbridge/intel/sandybridge/raminit_native.h"
27#include "southbridge/intel/bd82x6x/pch.h"
Patrick Rudolphe8e66f42016-02-06 17:42:42 +010028#include <southbridge/intel/common/gpio.h>
Vladimir Serbinenko55f3e2f2015-05-29 22:07:29 +020029#include <arch/cpu.h>
30#include <cpu/x86/msr.h>
Vladimir Serbinenkof06b08a2015-10-09 16:42:21 +020031#include <cbfs.h>
Vladimir Serbinenko55f3e2f2015-05-29 22:07:29 +020032
33void pch_enable_lpc(void)
34{
35 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
36 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
37 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
38 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
39 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
40 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
41 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
42}
43
44void rcba_config(void)
45{
46 /* Disable devices. */
47 RCBA32(0x3414) = 0x00000020;
48 RCBA32(0x3418) = 0x1ffc0ee3;
49
50}
51const struct southbridge_usb_port mainboard_usb_ports[] = {
52 { 1, 0, -1 },
53 { 1, 0, -1 },
54 { 1, 0, -1 },
55 { 1, 0, -1 },
56 { 1, 0, -1 },
57 { 1, 0, -1 },
58 { 1, 0, -1 },
59 { 1, 0, -1 },
60 { 1, 0, -1 },
61 { 1, 0, -1 },
62 { 1, 0, -1 },
63 { 1, 0, -1 },
64 { 1, 0, -1 },
65 { 1, 0, -1 },
66};
67
Vladimir Serbinenko609bd942016-01-31 14:00:54 +010068void mainboard_early_init(int s3resume) {
69}
70
Vladimir Serbinenkoffbb3c02016-02-10 01:36:25 +010071void mainboard_config_superio(void)
72{
73}
74
Kyösti Mälkkie258b9a2016-11-18 19:59:23 +020075void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Vladimir Serbinenko55f3e2f2015-05-29 22:07:29 +020076{
Vladimir Serbinenkof06b08a2015-10-09 16:42:21 +020077 void *spd_file;
78 size_t spd_file_len = 0;
79 spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
80 &spd_file_len);
81 if (spd_file && spd_file_len >= 1024) {
82 int i;
83 for (i = 0; i < 4; i++)
84 memcpy(&spd[i], spd_file + 256 * i, 128);
85 }
Vladimir Serbinenko55f3e2f2015-05-29 22:07:29 +020086}