blob: e1b667d54db86f7a7b27d7bccbc8eeee60f6cf7f [file] [log] [blame]
Vladimir Serbinenko55f3e2f2015-05-29 22:07:29 +02001#include <stdint.h>
2#include <string.h>
3#include <lib.h>
4#include <timestamp.h>
5#include <arch/byteorder.h>
6#include <arch/io.h>
7#include <device/pci_def.h>
8#include <device/pnp_def.h>
9#include <cpu/x86/lapic.h>
10#include <arch/acpi.h>
11#include <console/console.h>
12#include "northbridge/intel/sandybridge/sandybridge.h"
13#include "northbridge/intel/sandybridge/raminit_native.h"
14#include "southbridge/intel/bd82x6x/pch.h"
15#include "southbridge/intel/bd82x6x/gpio.h"
16#include <arch/cpu.h>
17#include <cpu/x86/msr.h>
18
19void pch_enable_lpc(void)
20{
21 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
22 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
23 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
24 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
25 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
26 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
27 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
28}
29
30void rcba_config(void)
31{
32 /* Disable devices. */
33 RCBA32(0x3414) = 0x00000020;
34 RCBA32(0x3418) = 0x1ffc0ee3;
35
36}
37const struct southbridge_usb_port mainboard_usb_ports[] = {
38 { 1, 0, -1 },
39 { 1, 0, -1 },
40 { 1, 0, -1 },
41 { 1, 0, -1 },
42 { 1, 0, -1 },
43 { 1, 0, -1 },
44 { 1, 0, -1 },
45 { 1, 0, -1 },
46 { 1, 0, -1 },
47 { 1, 0, -1 },
48 { 1, 0, -1 },
49 { 1, 0, -1 },
50 { 1, 0, -1 },
51 { 1, 0, -1 },
52};
53
54/* FIXME: Put proper SPD map here. */
55void mainboard_get_spd(spd_raw_data *spd)
56{
57 read_spd(&spd[0], 0x50);
58 read_spd(&spd[1], 0x51);
59 read_spd(&spd[2], 0x52);
60 read_spd(&spd[3], 0x53);
61}