Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Paul Menzel | a8ae1c6 | 2013-02-20 13:21:20 +0100 | [diff] [blame] | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 13 | * GNU General Public License for more details. |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 14 | */ |
efdesign98 | d7a696d | 2011-09-15 15:24:26 -0600 | [diff] [blame] | 15 | |
Kyösti Mälkki | 526c2fb | 2014-07-10 22:16:58 +0300 | [diff] [blame] | 16 | #include "AGESA.h" |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 17 | #include "amdlib.h" |
Kyösti Mälkki | 26f297e | 2014-05-26 11:27:54 +0300 | [diff] [blame] | 18 | #include <northbridge/amd/agesa/BiosCallOuts.h> |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 19 | #include "heapManager.h" |
| 20 | #include "SB800.h" |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 21 | #include <stdlib.h> |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 22 | |
Stefan Reinauer | dd132a5 | 2015-07-30 11:16:37 -0700 | [diff] [blame] | 23 | static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); |
| 24 | static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 25 | |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 26 | const BIOS_CALLOUT_STRUCT BiosCallouts[] = |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 27 | { |
Kyösti Mälkki | 5e19fa4 | 2014-05-04 23:13:54 +0300 | [diff] [blame] | 28 | {AGESA_DO_RESET, agesa_Reset }, |
Kyösti Mälkki | a1ebbc4 | 2014-10-17 22:33:22 +0300 | [diff] [blame] | 29 | {AGESA_READ_SPD, agesa_ReadSpd }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 30 | {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, |
Kyösti Mälkki | 6b4b151 | 2014-05-05 12:05:53 +0300 | [diff] [blame] | 31 | {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 32 | {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, |
| 33 | {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 34 | {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, |
| 35 | {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, |
| 36 | {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 37 | }; |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 38 | const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 39 | |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 40 | /* Call the host environment interface to provide a user hook opportunity. */ |
Stefan Reinauer | dd132a5 | 2015-07-30 11:16:37 -0700 | [diff] [blame] | 41 | static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 42 | { |
Jens Rottmann | 384ee9f | 2013-02-18 20:26:50 +0100 | [diff] [blame] | 43 | // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. |
| 44 | // Make sure the right speed settings are selected. |
| 45 | ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; |
| 46 | return AGESA_SUCCESS; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 47 | } |
efdesign98 | d7a696d | 2011-09-15 15:24:26 -0600 | [diff] [blame] | 48 | |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 49 | /* PCIE slot reset control */ |
Stefan Reinauer | dd132a5 | 2015-07-30 11:16:37 -0700 | [diff] [blame] | 50 | static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 51 | { |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 52 | AGESA_STATUS Status; |
| 53 | UINTN FcnData; |
| 54 | PCIe_SLOT_RESET_INFO *ResetInfo; |
efdesign98 | d7a696d | 2011-09-15 15:24:26 -0600 | [diff] [blame] | 55 | |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 56 | UINT32 GpioMmioAddr; |
| 57 | UINT32 AcpiMmioAddr; |
| 58 | UINT8 Data8; |
| 59 | UINT16 Data16; |
efdesign98 | d7a696d | 2011-09-15 15:24:26 -0600 | [diff] [blame] | 60 | |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 61 | FcnData = Data; |
| 62 | ResetInfo = ConfigPtr; |
| 63 | // Get SB800 MMIO Base (AcpiMmioAddr) |
| 64 | WriteIo8(0xCD6, 0x27); |
| 65 | Data8 = ReadIo8(0xCD7); |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame] | 66 | Data16 = Data8 << 8; |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 67 | WriteIo8(0xCD6, 0x26); |
| 68 | Data8 = ReadIo8(0xCD7); |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame] | 69 | Data16 |= Data8; |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 70 | AcpiMmioAddr = (UINT32)Data16 << 16; |
| 71 | Status = AGESA_UNSUPPORTED; |
| 72 | GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; |
| 73 | switch (ResetInfo->ResetId) |
| 74 | { |
Jens Rottmann | fa8702c | 2013-02-18 19:40:33 +0100 | [diff] [blame] | 75 | case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 76 | switch (ResetInfo->ResetControl) { |
zbao | afd141d | 2012-03-30 15:32:07 +0800 | [diff] [blame] | 77 | case AssertSlotReset: |
Jens Rottmann | fa8702c | 2013-02-18 19:40:33 +0100 | [diff] [blame] | 78 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); |
Elyes HAOUAS | f2fcf22 | 2016-10-02 10:09:11 +0200 | [diff] [blame] | 79 | Data8 &= ~(UINT8)BIT6; |
Jens Rottmann | fa8702c | 2013-02-18 19:40:33 +0100 | [diff] [blame] | 80 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 81 | Status = AGESA_SUCCESS; |
| 82 | break; |
zbao | afd141d | 2012-03-30 15:32:07 +0800 | [diff] [blame] | 83 | case DeassertSlotReset: |
Jens Rottmann | fa8702c | 2013-02-18 19:40:33 +0100 | [diff] [blame] | 84 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); |
Elyes HAOUAS | f2fcf22 | 2016-10-02 10:09:11 +0200 | [diff] [blame] | 85 | Data8 |= BIT6; |
Jens Rottmann | fa8702c | 2013-02-18 19:40:33 +0100 | [diff] [blame] | 86 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 87 | Status = AGESA_SUCCESS; |
| 88 | break; |
| 89 | } |
| 90 | break; |
| 91 | } |
| 92 | return Status; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 93 | } |