Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Paul Menzel | a8ae1c6 | 2013-02-20 13:21:20 +0100 | [diff] [blame] | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 18 | */ |
efdesign98 | d7a696d | 2011-09-15 15:24:26 -0600 | [diff] [blame] | 19 | |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 20 | #include "agesawrapper.h" |
| 21 | #include "amdlib.h" |
| 22 | #include "BiosCallOuts.h" |
| 23 | #include "heapManager.h" |
| 24 | #include "SB800.h" |
Martin Roth | 45f72ce | 2013-02-24 12:58:33 -0700 | [diff] [blame] | 25 | #include <northbridge/amd/agesa/family14/dimmSpd.h> |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame^] | 26 | #include <stdlib.h> |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 27 | |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 28 | static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); |
| 29 | static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); |
| 30 | |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame^] | 31 | const BIOS_CALLOUT_STRUCT BiosCallouts[] = |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 32 | { |
Kyösti Mälkki | 08df732 | 2014-05-04 14:53:36 +0300 | [diff] [blame] | 33 | {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, |
| 34 | {AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer }, |
Kyösti Mälkki | 08df732 | 2014-05-04 14:53:36 +0300 | [diff] [blame] | 35 | {AGESA_LOCATE_BUFFER, BiosLocateBuffer }, |
Kyösti Mälkki | 5e19fa4 | 2014-05-04 23:13:54 +0300 | [diff] [blame] | 36 | {AGESA_DO_RESET, agesa_Reset }, |
Kyösti Mälkki | 08df732 | 2014-05-04 14:53:36 +0300 | [diff] [blame] | 37 | {AGESA_READ_SPD, BiosReadSpd }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 38 | {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, |
Kyösti Mälkki | 6b4b151 | 2014-05-05 12:05:53 +0300 | [diff] [blame] | 39 | {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 40 | {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, |
| 41 | {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 42 | {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, |
| 43 | {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, |
| 44 | {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 45 | }; |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame^] | 46 | const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 47 | |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 48 | /* Call the host environment interface to provide a user hook opportunity. */ |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 49 | static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 50 | { |
Jens Rottmann | 384ee9f | 2013-02-18 20:26:50 +0100 | [diff] [blame] | 51 | // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. |
| 52 | // Make sure the right speed settings are selected. |
| 53 | ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; |
| 54 | return AGESA_SUCCESS; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 55 | } |
efdesign98 | d7a696d | 2011-09-15 15:24:26 -0600 | [diff] [blame] | 56 | |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 57 | /* PCIE slot reset control */ |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 58 | static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 59 | { |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 60 | AGESA_STATUS Status; |
| 61 | UINTN FcnData; |
| 62 | PCIe_SLOT_RESET_INFO *ResetInfo; |
efdesign98 | d7a696d | 2011-09-15 15:24:26 -0600 | [diff] [blame] | 63 | |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 64 | UINT32 GpioMmioAddr; |
| 65 | UINT32 AcpiMmioAddr; |
| 66 | UINT8 Data8; |
| 67 | UINT16 Data16; |
efdesign98 | d7a696d | 2011-09-15 15:24:26 -0600 | [diff] [blame] | 68 | |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 69 | FcnData = Data; |
| 70 | ResetInfo = ConfigPtr; |
| 71 | // Get SB800 MMIO Base (AcpiMmioAddr) |
| 72 | WriteIo8(0xCD6, 0x27); |
| 73 | Data8 = ReadIo8(0xCD7); |
| 74 | Data16=Data8<<8; |
| 75 | WriteIo8(0xCD6, 0x26); |
| 76 | Data8 = ReadIo8(0xCD7); |
| 77 | Data16|=Data8; |
| 78 | AcpiMmioAddr = (UINT32)Data16 << 16; |
| 79 | Status = AGESA_UNSUPPORTED; |
| 80 | GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; |
| 81 | switch (ResetInfo->ResetId) |
| 82 | { |
Jens Rottmann | fa8702c | 2013-02-18 19:40:33 +0100 | [diff] [blame] | 83 | case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 84 | switch (ResetInfo->ResetControl) { |
zbao | afd141d | 2012-03-30 15:32:07 +0800 | [diff] [blame] | 85 | case AssertSlotReset: |
Jens Rottmann | fa8702c | 2013-02-18 19:40:33 +0100 | [diff] [blame] | 86 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 87 | Data8 &= ~(UINT8)BIT6 ; |
Jens Rottmann | fa8702c | 2013-02-18 19:40:33 +0100 | [diff] [blame] | 88 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 89 | Status = AGESA_SUCCESS; |
| 90 | break; |
zbao | afd141d | 2012-03-30 15:32:07 +0800 | [diff] [blame] | 91 | case DeassertSlotReset: |
Jens Rottmann | fa8702c | 2013-02-18 19:40:33 +0100 | [diff] [blame] | 92 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 93 | Data8 |= BIT6 ; |
Jens Rottmann | fa8702c | 2013-02-18 19:40:33 +0100 | [diff] [blame] | 94 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); |
Marc Jones | 36abff1 | 2011-11-07 23:26:14 -0700 | [diff] [blame] | 95 | Status = AGESA_SUCCESS; |
| 96 | break; |
| 97 | } |
| 98 | break; |
| 99 | } |
| 100 | return Status; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 101 | } |