Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2010 Nils Jacobs |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Paul Menzel | a8ae1c6 | 2013-02-20 13:21:20 +0100 | [diff] [blame] | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 18 | * Foundation, Inc. |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 21 | #include <console/console.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <stdint.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <stdlib.h> |
| 28 | #include <string.h> |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 29 | #include "northbridge.h" |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 30 | #include <cpu/x86/msr.h> |
| 31 | #include <cpu/x86/cache.h> |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 32 | #include <cpu/amd/vr.h> |
Corey Osgood | e562f72 | 2008-12-19 03:36:48 +0000 | [diff] [blame] | 33 | #include <cpu/cpu.h> |
Marc Jones | 08da4f1 | 2007-05-04 19:09:01 +0000 | [diff] [blame] | 34 | #include "../../../southbridge/amd/cs5536/cs5536.h" |
Ronald G. Minnich | 36c00aa | 2006-04-18 22:40:53 +0000 | [diff] [blame] | 35 | |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 36 | void print_conf(void); |
| 37 | |
| 38 | /* Print the platform configuration - do before PCI init or it will not |
| 39 | * work right. |
| 40 | */ |
| 41 | void print_conf(void) |
| 42 | { |
| 43 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR |
| 44 | int i; |
| 45 | unsigned long iol; |
| 46 | msr_t msr; |
| 47 | |
| 48 | int cpu_msr_defs[] = { CPU_IM_CONFIG, CPU_DM_CONFIG0, |
| 49 | CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, |
| 50 | CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM, |
| 51 | GLCP_DELAY_CONTROLS, GL_END |
| 52 | }; |
| 53 | |
| 54 | int gliu0_msr_defs[] = { GLIU0_P2D_BM_0, GLIU0_P2D_BM_1, |
| 55 | GLIU0_P2D_BM_2, GLIU0_P2D_BM_3, GLIU0_P2D_BM_4, |
| 56 | GLIU0_P2D_BM_5, GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, |
| 57 | GLIU0_P2D_R_0, GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, |
| 58 | GLIU0_P2D_RO_2, GLIU0_P2D_SC_0, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, |
| 59 | GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, |
| 60 | GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, |
| 61 | GLIU0_GLD_MSR_COH, GL_END |
| 62 | }; |
| 63 | |
| 64 | int gliu1_msr_defs[] = { GLIU1_P2D_BM_0, GLIU1_P2D_BM_1, |
| 65 | GLIU1_P2D_BM_2, GLIU1_P2D_BM_3, GLIU1_P2D_BM_4, |
| 66 | GLIU1_P2D_BM_5, GLIU1_P2D_BM_6, GLIU1_P2D_BM_7, |
| 67 | GLIU1_P2D_BM_8, GLIU1_P2D_R_0, GLIU1_P2D_R_1, |
| 68 | GLIU1_P2D_R_2, GLIU1_P2D_R_3, GLIU1_P2D_SC_0, |
| 69 | GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0, |
| 70 | GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, GLIU1_IOD_SC_4, |
| 71 | GLIU1_IOD_SC_5, GLIU1_GLD_MSR_COH, GL_END |
| 72 | }; |
| 73 | |
| 74 | int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, |
| 75 | CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END |
| 76 | }; |
| 77 | |
| 78 | int lbar_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, GL_END |
| 79 | }; |
| 80 | |
| 81 | int irq_msr[] = { MDD_IRQM_YLOW, MDD_IRQM_YHIGH, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, |
| 82 | MDD_IRQM_PRIM, GL_END |
| 83 | }; |
| 84 | |
| 85 | int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, |
| 86 | GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, |
| 87 | GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END |
| 88 | }; |
| 89 | |
| 90 | int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, |
| 91 | MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6, |
| 92 | MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END |
| 93 | }; |
| 94 | |
| 95 | printk(BIOS_DEBUG, "---------- CPU ------------\n"); |
| 96 | |
| 97 | for (i = 0; cpu_msr_defs[i] != GL_END; i++) { |
| 98 | msr = rdmsr(cpu_msr_defs[i]); |
| 99 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", |
| 100 | cpu_msr_defs[i], msr.hi, msr.lo); |
| 101 | } |
| 102 | |
| 103 | printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n"); |
| 104 | |
| 105 | for (i = 0; gliu0_msr_defs[i] != GL_END; i++) { |
| 106 | msr = rdmsr(gliu0_msr_defs[i]); |
| 107 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", |
| 108 | gliu0_msr_defs[i], msr.hi, msr.lo); |
| 109 | } |
| 110 | |
| 111 | printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n"); |
| 112 | |
| 113 | for (i = 0; gliu1_msr_defs[i] != GL_END; i++) { |
| 114 | msr = rdmsr(gliu1_msr_defs[i]); |
| 115 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", |
| 116 | gliu1_msr_defs[i], msr.hi, msr.lo); |
| 117 | } |
| 118 | |
| 119 | printk(BIOS_DEBUG, "---------- RCONF ------------\n"); |
| 120 | |
| 121 | for (i = 0; rconf_msr[i] != GL_END; i++) { |
| 122 | msr = rdmsr(rconf_msr[i]); |
| 123 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], |
| 124 | msr.hi, msr.lo); |
| 125 | } |
| 126 | |
| 127 | printk(BIOS_DEBUG, "---------- VARIA ------------\n"); |
| 128 | msr = rdmsr(ATA_SB_IDE_CFG); |
| 129 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", ATA_SB_IDE_CFG, msr.hi, |
| 130 | msr.lo); |
| 131 | |
| 132 | msr = rdmsr(MDD_LEG_IO); |
| 133 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_LEG_IO, msr.hi, |
| 134 | msr.lo); |
| 135 | |
| 136 | msr = rdmsr(MDD_PIN_OPT); |
| 137 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_PIN_OPT, msr.hi, |
| 138 | msr.lo); |
| 139 | |
| 140 | printk(BIOS_DEBUG, "---------- PCI ------------\n"); |
| 141 | |
| 142 | for (i = 0; pci_msr[i] != GL_END; i++) { |
| 143 | msr = rdmsr(pci_msr[i]); |
| 144 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], |
| 145 | msr.hi, msr.lo); |
| 146 | } |
| 147 | |
| 148 | printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n"); |
| 149 | |
| 150 | for (i = 0; dma_msr[i] != GL_END; i++) { |
| 151 | msr = rdmsr(dma_msr[i]); |
| 152 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], |
| 153 | msr.hi, msr.lo); |
| 154 | } |
| 155 | |
| 156 | printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n"); |
| 157 | |
| 158 | for (i = 0; irq_msr[i] != GL_END; i++) { |
| 159 | msr = rdmsr(irq_msr[i]); |
| 160 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", irq_msr[i], |
| 161 | msr.hi, msr.lo); |
| 162 | } |
| 163 | |
| 164 | printk(BIOS_DEBUG, "---------- DIVIL LBAR -----------\n"); |
| 165 | |
| 166 | for (i = 0; lbar_msr[i] != GL_END; i++) { |
| 167 | msr = rdmsr(lbar_msr[i]); |
| 168 | printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", lbar_msr[i], |
| 169 | msr.hi, msr.lo); |
| 170 | } |
| 171 | |
| 172 | iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); |
| 173 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", |
| 174 | GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); |
| 175 | iol = inl(GPIOL_EVENTS_ENABLE); |
| 176 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", |
| 177 | GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); |
| 178 | iol = inl(GPIOL_INPUT_INVERT_ENABLE); |
| 179 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", |
| 180 | GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); |
| 181 | iol = inl(GPIO_MAPPER_X); |
| 182 | printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X, |
| 183 | iol); |
| 184 | #endif /* CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR */ |
| 185 | } |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 186 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 187 | /* todo: add a resource record. We don't do this here because this may be called when |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 188 | * very little of the platform is actually working. |
| 189 | */ |
| 190 | int sizeram(void) |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 191 | { |
| 192 | msr_t msr; |
Ronald G. Minnich | cd6985b | 2006-03-21 23:24:33 +0000 | [diff] [blame] | 193 | int sizem = 0; |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 194 | unsigned short dimm; |
| 195 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 196 | /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */ |
Nils Jacobs | 3344743 | 2010-12-26 05:16:47 +0000 | [diff] [blame] | 197 | msr = rdmsr(MC_CF07_DATA); |
| 198 | printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo); |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 199 | |
| 200 | /* dimm 0 */ |
| 201 | dimm = msr.hi; |
| 202 | /* installed? */ |
| 203 | if ((dimm & 7) != 7) |
| 204 | sizem = (1 << ((dimm >> 12)-1)) * 8; |
| 205 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 206 | /* dimm 1 */ |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 207 | dimm = msr.hi >> 16; |
| 208 | /* installed? */ |
| 209 | if ((dimm & 7) != 7) |
| 210 | sizem += (1 << ((dimm >> 12)-1)) * 8; |
| 211 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 212 | printk(BIOS_DEBUG, "sizeram: sizem 0x%x\n", sizem); |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 213 | return sizem; |
| 214 | } |
| 215 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 216 | static void enable_shadow(device_t dev) |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 217 | { |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 218 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 219 | } |
| 220 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 221 | static void northbridge_init(device_t dev) |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 222 | { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 223 | printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 224 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 225 | enable_shadow(dev); |
| 226 | } |
| 227 | |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 228 | static void northbridge_set_resources(struct device *dev) |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame] | 229 | { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 230 | uint8_t line; |
| 231 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 232 | struct bus *bus; |
Stefan Reinauer | 4154c66 | 2010-04-14 10:12:23 +0000 | [diff] [blame] | 233 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 234 | for(bus = dev->link_list; bus; bus = bus->next) { |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 235 | if (bus->children) { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 236 | printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n", |
| 237 | bus->secondary); |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 238 | assign_resources(bus); |
| 239 | } |
| 240 | } |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame] | 241 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 242 | /* set a default latency timer */ |
| 243 | pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame] | 244 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 245 | /* set a default secondary latency timer */ |
| 246 | if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { |
| 247 | pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); |
| 248 | } |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame] | 249 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 250 | /* zero the irq settings */ |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 251 | line = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 252 | if (line) { |
| 253 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); |
| 254 | } |
| 255 | /* set the cache line size, so far 64 bytes is good for everyone */ |
| 256 | pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame] | 257 | } |
| 258 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 259 | static struct device_operations northbridge_operations = { |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 260 | .read_resources = pci_dev_read_resources, |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 261 | .set_resources = northbridge_set_resources, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 262 | .enable_resources = pci_dev_enable_resources, |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 263 | .init = northbridge_init, |
| 264 | .enable = 0, |
| 265 | .ops_pci = 0, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 266 | }; |
| 267 | |
Stefan Reinauer | f1cf1f7 | 2007-10-24 09:08:58 +0000 | [diff] [blame] | 268 | static const struct pci_driver northbridge_driver __pci_driver = { |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 269 | .ops = &northbridge_operations, |
Li-Ta Lo | 05c0869 | 2006-04-20 21:26:01 +0000 | [diff] [blame] | 270 | .vendor = PCI_VENDOR_ID_NS, |
| 271 | .device = PCI_DEVICE_ID_NS_GX2, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 272 | }; |
| 273 | |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 274 | #include <cbmem.h> |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 275 | |
| 276 | static void pci_domain_set_resources(device_t dev) |
| 277 | { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 278 | int idx; |
| 279 | u32 tomk; |
| 280 | device_t mc_dev; |
| 281 | |
| 282 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); |
| 283 | |
| 284 | mc_dev = dev->link_list->children; |
| 285 | if (mc_dev) { |
| 286 | tomk = get_systop() / 1024; |
| 287 | /* Report the memory regions |
| 288 | All memory up to systop except 0xa0000-0xbffff */ |
| 289 | idx = 10; |
| 290 | ram_resource(dev, idx++, 0, 640); |
| 291 | ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */ |
| 292 | |
Kyösti Mälkki | 42f4651 | 2013-06-27 08:20:09 +0300 | [diff] [blame] | 293 | set_top_of_ram(tomk * 1024); |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 294 | } |
| 295 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 296 | assign_resources(dev->link_list); |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 297 | } |
| 298 | |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 299 | static void pci_domain_enable(device_t dev) |
| 300 | { |
| 301 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); |
| 302 | |
| 303 | /* do this here for now -- this chip really breaks our device model */ |
| 304 | northbridge_init_early(); |
| 305 | cpubug(); |
| 306 | chipsetinit(); |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 307 | print_conf(); |
| 308 | do_vsmbios(); |
| 309 | graphics_init(); |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 310 | } |
| 311 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 312 | static struct device_operations pci_domain_ops = { |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 313 | .read_resources = pci_domain_read_resources, |
| 314 | .set_resources = pci_domain_set_resources, |
| 315 | .enable_resources = NULL, |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 316 | .scan_bus = pci_domain_scan_bus, |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 317 | .enable = pci_domain_enable, |
Kyösti Mälkki | 33e5df3 | 2013-07-03 10:51:34 +0300 | [diff] [blame] | 318 | .ops_pci_bus = pci_bus_default_ops, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 319 | }; |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 320 | |
| 321 | static void cpu_bus_init(device_t dev) |
| 322 | { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 323 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); |
| 324 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 325 | initialize_cpus(dev->link_list); |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 326 | } |
| 327 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 328 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 812d2a4 | 2014-10-31 08:17:23 +1100 | [diff] [blame] | 329 | .read_resources = DEVICE_NOOP, |
| 330 | .set_resources = DEVICE_NOOP, |
| 331 | .enable_resources = DEVICE_NOOP, |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 332 | .init = cpu_bus_init, |
| 333 | .scan_bus = 0, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 334 | }; |
| 335 | |
| 336 | static void enable_dev(struct device *dev) |
| 337 | { |
Nils Jacobs | 84be0f5 | 2010-12-29 21:12:10 +0000 | [diff] [blame] | 338 | printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n", |
| 339 | __func__, dev->path.type); |
Stefan Reinauer | ba09695 | 2010-04-22 09:22:15 +0000 | [diff] [blame] | 340 | |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 341 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 342 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 343 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 344 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Nils Jacobs | 1c6d4e6 | 2010-12-26 05:12:49 +0000 | [diff] [blame] | 345 | dev->ops = &cpu_bus_ops; |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | struct chip_operations northbridge_amd_gx2_ops = { |
Uwe Hermann | a7aa29b | 2006-11-05 18:50:49 +0000 | [diff] [blame] | 349 | CHIP_NAME("AMD GX (previously GX2) Northbridge") |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 350 | .enable_dev = enable_dev, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 351 | }; |