Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 1 | #include <console/console.h> |
| 2 | #include <arch/io.h> |
| 3 | #include <stdint.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
| 7 | #include <stdlib.h> |
| 8 | #include <string.h> |
| 9 | #include <bitops.h> |
| 10 | #include "chip.h" |
| 11 | #include "northbridge.h" |
| 12 | #include <cpu/amd/gx2def.h> |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 13 | #include <cpu/x86/msr.h> |
| 14 | #include <cpu/x86/cache.h> |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 15 | #include <cpu/amd/vr.h> |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 16 | #define VIDEO_MB 8 |
Ronald G. Minnich | 36c00aa | 2006-04-18 22:40:53 +0000 | [diff] [blame] | 17 | |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 18 | extern void graphics_init(void); |
| 19 | |
| 20 | #define NORTHBRIDGE_FILE "northbridge.c" |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 21 | |
| 22 | /* todo: add a resource record. We don't do this here because this may be called when |
| 23 | * very little of the platform is actually working. |
| 24 | */ |
| 25 | int |
| 26 | sizeram(void) |
| 27 | { |
| 28 | msr_t msr; |
Ronald G. Minnich | cd6985b | 2006-03-21 23:24:33 +0000 | [diff] [blame] | 29 | int sizem = 0; |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 30 | unsigned short dimm; |
| 31 | |
| 32 | msr = rdmsr(0x20000018); |
| 33 | printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo); |
| 34 | |
| 35 | /* dimm 0 */ |
| 36 | dimm = msr.hi; |
| 37 | /* installed? */ |
| 38 | if ((dimm & 7) != 7) |
| 39 | sizem = (1 << ((dimm >> 12)-1)) * 8; |
| 40 | |
| 41 | |
| 42 | /* dimm 1*/ |
| 43 | dimm = msr.hi >> 16; |
| 44 | /* installed? */ |
| 45 | if ((dimm & 7) != 7) |
| 46 | sizem += (1 << ((dimm >> 12)-1)) * 8; |
| 47 | |
| 48 | printk_debug("sizeram: sizem 0x%x\n", sizem); |
| 49 | return sizem; |
| 50 | } |
| 51 | |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 52 | |
| 53 | /* here is programming for the various MSRs.*/ |
| 54 | #define IM_QWAIT 0x100000 |
| 55 | |
| 56 | #define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */ |
| 57 | #define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */ |
| 58 | |
| 59 | /* these are the 8-bit attributes for controlling RCONF registers */ |
| 60 | #define CACHE_DISABLE (1<<0) |
| 61 | #define WRITE_ALLOCATE (1<<1) |
| 62 | #define WRITE_PROTECT (1<<2) |
| 63 | #define WRITE_THROUGH (1<<3) |
| 64 | #define WRITE_COMBINE (1<<4) |
| 65 | #define WRITE_SERIALIZE (1<<5) |
| 66 | |
| 67 | /* ram has none of this stuff */ |
| 68 | #define RAM_PROPERTIES (0) |
| 69 | #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) |
Ronald G. Minnich | 53a00b7 | 2006-06-23 03:39:10 +0000 | [diff] [blame] | 70 | #define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 71 | #define MSR_WS_CD_DEFAULT (0x21212121) |
| 72 | |
| 73 | /* 1810-1817 give you 8 registers with which to program protection regions */ |
| 74 | /* the are region configuration range registers, or RRCF */ |
| 75 | /* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */ |
| 76 | /* so no left-shift needed for top or base */ |
| 77 | #define RRCF_LOW(base,properties) (base|(1<<8)|properties) |
| 78 | #define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE) |
| 79 | |
| 80 | /* build initializer for P2D MSR */ |
| 81 | #define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}} |
| 82 | #define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}} |
| 83 | #define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}} |
| 84 | #define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}} |
| 85 | #define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}} |
| 86 | #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} |
| 87 | #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} |
| 88 | |
| 89 | |
| 90 | |
| 91 | struct msr_defaults { |
| 92 | int msr_no; |
| 93 | msr_t msr; |
| 94 | } msr_defaults [] = { |
| 95 | {0x1700, {.hi = 0, .lo = IM_QWAIT}}, |
| 96 | {0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}}, |
| 97 | /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */ |
| 98 | /* for 180a, for now, we assume VSM will configure it */ |
| 99 | /* 180b is left at reset value,a0000-bffff is non-cacheable */ |
| 100 | /* 180c, c0000-dffff is set to write serialize and non-cachable */ |
| 101 | /* oops, 180c will be set by cpu bug handling in cpubug.c */ |
| 102 | //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, |
| 103 | /* 180d is left at default, e0000-fffff is non-cached */ |
| 104 | |
| 105 | /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ |
| 106 | /* we will not set 0x180f, the DMM,yet */ |
| 107 | //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, |
| 108 | //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, |
| 109 | //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, |
| 110 | //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, |
| 111 | /* now for GLPCI routing */ |
| 112 | /* GLIU0 */ |
| 113 | P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80), |
| 114 | P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0), |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 115 | P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0xC0000), |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 116 | /* GLIU1 */ |
| 117 | P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80), |
| 118 | P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0), |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 119 | P2D_SC(0x4000002d, 0x1, 0x0, 0x0, 0xff03, 0xC0000), |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 120 | {0} |
| 121 | }; |
| 122 | |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 123 | /* note that dev is NOT used -- yet */ |
| 124 | static void irq_init_steering(struct device *dev, uint16_t irq_map) { |
| 125 | /* Set up IRQ steering */ |
| 126 | uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; |
| 127 | |
| 128 | printk_debug("%s(%08X [%08X], %04X)\n", __FUNCTION__, dev, pciAddr, irq_map); |
| 129 | |
| 130 | /* The IRQ steering values (in hex) are effectively dcba, where: |
| 131 | * <a> represents the IRQ for INTA, |
| 132 | * <b> represents the IRQ for INTB, |
| 133 | * <c> represents the IRQ for INTC, and |
| 134 | * <d> represents the IRQ for INTD. |
| 135 | * Thus, a value of irq_map = 0xAA5B translates to: |
| 136 | * INTA = IRQB (IRQ 11) |
| 137 | * INTB = IRQ5 (IRQ 5) |
| 138 | * INTC = IRQA (IRQ 10) |
| 139 | * INTD = IRQA (IRQ 10) |
| 140 | */ |
| 141 | outl(pciAddr & ~3, 0xCF8); |
| 142 | outl(irq_map, 0xCFC); |
| 143 | } |
| 144 | |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 145 | |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 146 | /* |
| 147 | * setup_gx2_cache |
| 148 | * |
| 149 | * Returns the amount of memory (in KB) available to the system. This is the |
| 150 | * total amount of memory less the amount of memory reserved for SMM use. |
| 151 | * |
| 152 | */ |
Ronald G. Minnich | 1a971bd | 2006-03-22 17:30:48 +0000 | [diff] [blame] | 153 | static int |
| 154 | setup_gx2_cache(void) |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 155 | { |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 156 | msr_t msr; |
| 157 | unsigned long long val; |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 158 | int sizekbytes, sizereg; |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 159 | |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 160 | sizekbytes = sizeram() * 1024; |
| 161 | printk_debug("setup_gx2_cache: enable for %d KB\n", sizekbytes); |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 162 | /* build up the rconf word. */ |
| 163 | /* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */ |
| 164 | /* set romrp */ |
| 165 | val = ((unsigned long long) ROM_PROPERTIES) << 56; |
| 166 | /* make rom base useful for 1M roms */ |
Ronald G. Minnich | 98e904e | 2006-05-15 04:44:15 +0000 | [diff] [blame] | 167 | /* Flash base address -- sized for 1M for now*/ |
| 168 | val |= ((unsigned long long) 0xfff00)<<36; |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 169 | /* set the devrp properties */ |
| 170 | val |= ((unsigned long long) DEVICE_PROPERTIES) << 28; |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 171 | /* Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */ |
| 172 | /* yank off memory for the SMM handler */ |
| 173 | sizekbytes -= SMM_SIZE; |
| 174 | sizereg = sizekbytes; |
| 175 | sizereg *= 1024; // convert to bytes |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 176 | sizereg >>= 12; |
| 177 | sizereg <<= 8; |
| 178 | val |= sizereg; |
| 179 | val |= RAM_PROPERTIES; |
| 180 | msr.lo = val; |
| 181 | msr.hi = (val >> 32); |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 182 | printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo); |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 183 | wrmsr(CPU_RCONF_DEFAULT, msr); |
| 184 | |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 185 | enable_cache(); |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 186 | wbinvd(); |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 187 | return sizekbytes; |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 188 | } |
Li-Ta Lo | 8854d30 | 2006-04-03 22:20:05 +0000 | [diff] [blame] | 189 | |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 190 | /* we have to do this here. We have not found a nicer way to do it */ |
| 191 | void |
| 192 | setup_gx2(void) |
| 193 | { |
Ronald G. Minnich | 48415d5 | 2006-06-18 01:29:42 +0000 | [diff] [blame] | 194 | |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 195 | unsigned long tmp, tmp2; |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 196 | msr_t msr; |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 197 | unsigned long size_kb, membytes; |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 198 | |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 199 | size_kb = setup_gx2_cache(); |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 200 | |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 201 | membytes = size_kb * 1024; |
Ronald G. Minnich | 98e904e | 2006-05-15 04:44:15 +0000 | [diff] [blame] | 202 | /* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST! |
| 203 | * so it is safe to use. You should NOT at this point call |
| 204 | * sizeram() directly. |
| 205 | */ |
| 206 | |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 207 | /* we need to set 0x10000028 and 0x40000029 */ |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 208 | /* |
| 209 | * These two descriptors cover the range from 1 MB (0x100000) to |
| 210 | * SYSTOP (a.k.a. TOM, or Top of Memory) |
| 211 | */ |
| 212 | |
| 213 | #if 0 |
| 214 | /* This has already been done elsewhere */ |
| 215 | printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes); |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 216 | msr.hi = 0x20000000 | membytes>>24; |
| 217 | msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20); |
| 218 | wrmsr(0x10000028, msr); |
| 219 | msr.hi = 0x20000000 | membytes>>24; |
| 220 | msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20); |
| 221 | wrmsr(0x40000029, msr); |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 222 | #endif |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 223 | #if 0 |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 224 | msr = rdmsr(0x10000028); |
| 225 | printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo); |
| 226 | msr = rdmsr(0x40000029); |
| 227 | printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo); |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 228 | #endif |
Ronald G. Minnich | 98e904e | 2006-05-15 04:44:15 +0000 | [diff] [blame] | 229 | #if 1 |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 230 | /* fixme: SMM MSR 0x10000026 and 0x400000023 */ |
| 231 | /* calculate the OFFSET field */ |
| 232 | tmp = membytes - SMM_OFFSET; |
| 233 | tmp >>= 12; |
| 234 | tmp <<= 8; |
| 235 | tmp |= 0x20000000; |
| 236 | tmp |= (SMM_OFFSET >> 24); |
| 237 | |
| 238 | /* calculate the PBASE and PMASK fields */ |
| 239 | tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */ |
| 240 | tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff); |
| 241 | printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2); |
| 242 | msr.hi = tmp; |
| 243 | msr.lo = tmp2; |
| 244 | wrmsr(0x10000026, msr); |
Ronald G. Minnich | 98e904e | 2006-05-15 04:44:15 +0000 | [diff] [blame] | 245 | #endif |
| 246 | #if 0 |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 247 | |
| 248 | msr.hi = 0x2cfbc040; |
| 249 | msr.lo = 0x400fffc0; |
| 250 | wrmsr(0x10000026, msr); |
| 251 | msr = rdmsr(0x10000026); |
| 252 | printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo); |
Ronald G. Minnich | 98e904e | 2006-05-15 04:44:15 +0000 | [diff] [blame] | 253 | #endif |
| 254 | #if 0 |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 255 | msr.hi = 0x22fffc02; |
| 256 | msr.lo = 0x10ffbf00; |
| 257 | wrmsr(0x1808, msr); |
| 258 | msr = rdmsr(0x1808); |
| 259 | printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo); |
| 260 | #endif |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 261 | #if 0 // SDG - don't do this |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 262 | /* now do the default MSR values */ |
| 263 | for(i = 0; msr_defaults[i].msr_no; i++) { |
| 264 | msr_t msr; |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 265 | wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 266 | msr = rdmsr(msr_defaults[i].msr_no); |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 267 | printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo); |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 268 | } |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 269 | #endif |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 270 | } |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 271 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 272 | static void enable_shadow(device_t dev) |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 273 | { |
| 274 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 275 | } |
| 276 | |
| 277 | static void northbridge_init(device_t dev) |
| 278 | { |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 279 | struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 280 | printk_debug("northbridge: %s()\n", __FUNCTION__); |
| 281 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 282 | enable_shadow(dev); |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 283 | irq_init_steering(dev, nb->irqmap); |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 284 | } |
| 285 | |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame^] | 286 | /* due to vsa interactions, we need not not touch the nb settings ... */ |
| 287 | /* this is a test -- we are not sure it will work -- but it ought to */ |
| 288 | static void set_resources(struct device *dev) |
| 289 | { |
| 290 | struct resource *resource, *last; |
| 291 | unsigned link; |
| 292 | uint8_t line; |
| 293 | |
| 294 | #if 0 |
| 295 | last = &dev->resource[dev->resources]; |
| 296 | |
| 297 | for(resource = &dev->resource[0]; resource < last; resource++) { |
| 298 | pci_set_resource(dev, resource); |
| 299 | } |
| 300 | #endif |
| 301 | for(link = 0; link < dev->links; link++) { |
| 302 | struct bus *bus; |
| 303 | bus = &dev->link[link]; |
| 304 | if (bus->children) { |
| 305 | assign_resources(bus); |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | #if 0 |
| 310 | /* set a default latency timer */ |
| 311 | pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); |
| 312 | |
| 313 | /* set a default secondary latency timer */ |
| 314 | if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { |
| 315 | pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); |
| 316 | } |
| 317 | |
| 318 | /* zero the irq settings */ |
| 319 | line = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
| 320 | if (line) { |
| 321 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); |
| 322 | } |
| 323 | /* set the cache line size, so far 64 bytes is good for everyone */ |
| 324 | pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); |
| 325 | #endif |
| 326 | } |
| 327 | |
| 328 | |
| 329 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 330 | static struct device_operations northbridge_operations = { |
| 331 | .read_resources = pci_dev_read_resources, |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame^] | 332 | #if 0 |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 333 | .set_resources = pci_dev_set_resources, |
Ronald G. Minnich | 08af3f5 | 2006-08-09 02:21:49 +0000 | [diff] [blame^] | 334 | #endif |
| 335 | .set_resources = set_resources, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 336 | .enable_resources = pci_dev_enable_resources, |
| 337 | .init = northbridge_init, |
| 338 | .enable = 0, |
| 339 | .ops_pci = 0, |
| 340 | }; |
| 341 | |
| 342 | static struct pci_driver northbridge_driver __pci_driver = { |
| 343 | .ops = &northbridge_operations, |
Li-Ta Lo | 05c0869 | 2006-04-20 21:26:01 +0000 | [diff] [blame] | 344 | .vendor = PCI_VENDOR_ID_NS, |
| 345 | .device = PCI_DEVICE_ID_NS_GX2, |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 346 | }; |
| 347 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 348 | #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) |
| 349 | |
| 350 | static void pci_domain_read_resources(device_t dev) |
| 351 | { |
| 352 | struct resource *resource; |
| 353 | |
| 354 | printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__); |
| 355 | |
| 356 | /* Initialize the system wide io space constraints */ |
| 357 | resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); |
| 358 | resource->limit = 0xffffUL; |
| 359 | resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; |
| 360 | |
| 361 | /* Initialize the system wide memory resources constraints */ |
| 362 | resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); |
| 363 | resource->limit = 0xffffffffULL; |
| 364 | resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; |
| 365 | } |
| 366 | |
| 367 | static void ram_resource(device_t dev, unsigned long index, |
| 368 | unsigned long basek, unsigned long sizek) |
| 369 | { |
| 370 | struct resource *resource; |
| 371 | |
| 372 | if (!sizek) { |
| 373 | return; |
| 374 | } |
| 375 | resource = new_resource(dev, index); |
| 376 | resource->base = ((resource_t)basek) << 10; |
| 377 | resource->size = ((resource_t)sizek) << 10; |
| 378 | resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ |
| 379 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 380 | } |
| 381 | |
| 382 | static void tolm_test(void *gp, struct device *dev, struct resource *new) |
| 383 | { |
| 384 | struct resource **best_p = gp; |
| 385 | struct resource *best; |
| 386 | best = *best_p; |
| 387 | if (!best || (best->base > new->base)) { |
| 388 | best = new; |
| 389 | } |
| 390 | *best_p = best; |
| 391 | } |
| 392 | |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 393 | #if 0 |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 394 | static uint32_t find_pci_tolm(struct bus *bus) |
| 395 | { |
| 396 | struct resource *min; |
| 397 | uint32_t tolm; |
| 398 | min = 0; |
| 399 | search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); |
| 400 | tolm = 0xffffffffUL; |
| 401 | if (min && tolm > min->base) { |
| 402 | tolm = min->base; |
| 403 | } |
| 404 | return tolm; |
| 405 | } |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 406 | #endif |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 407 | #define FRAMEBUFFERK 4096 |
| 408 | |
| 409 | static void pci_domain_set_resources(device_t dev) |
| 410 | { |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 411 | #if 0 |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 412 | device_t mc_dev; |
| 413 | uint32_t pci_tolm; |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 414 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 415 | pci_tolm = find_pci_tolm(&dev->link[0]); |
| 416 | mc_dev = dev->link[0].children; |
| 417 | if (mc_dev) { |
| 418 | unsigned int tomk, tolmk; |
| 419 | unsigned int ramreg = 0; |
| 420 | int i, idx; |
| 421 | unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP); |
| 422 | unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD); |
| 423 | |
| 424 | for(i=0; i<0x20; i+= 0x10) { |
| 425 | unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG); |
| 426 | unsigned int mem_config = *mcreg; |
| 427 | |
| 428 | if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7) |
| 429 | continue; |
| 430 | ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2); |
| 431 | } |
| 432 | |
| 433 | tomk = ramreg << 10; |
| 434 | |
| 435 | /* Sort out the framebuffer size */ |
| 436 | tomk -= FRAMEBUFFERK; |
| 437 | *bcdramtop = ((tomk << 10) - 1); |
| 438 | *mcgbaseadd = (tomk >> 9); |
| 439 | |
| 440 | printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop); |
| 441 | printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd); |
| 442 | |
| 443 | printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10)); |
| 444 | |
| 445 | /* Compute the top of Low memory */ |
| 446 | tolmk = pci_tolm >> 10; |
| 447 | if (tolmk >= tomk) { |
| 448 | /* The PCI hole does does not overlap the memory. |
| 449 | */ |
| 450 | tolmk = tomk; |
| 451 | } |
| 452 | /* Report the memory regions */ |
| 453 | idx = 10; |
| 454 | ram_resource(dev, idx++, 0, tolmk); |
| 455 | } |
Li-Ta Lo | 108dd2c | 2006-02-23 21:39:19 +0000 | [diff] [blame] | 456 | #endif |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 457 | assign_resources(&dev->link[0]); |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 458 | } |
| 459 | |
| 460 | static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) |
| 461 | { |
| 462 | max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); |
| 463 | return max; |
| 464 | } |
| 465 | |
| 466 | static struct device_operations pci_domain_ops = { |
| 467 | .read_resources = pci_domain_read_resources, |
| 468 | .set_resources = pci_domain_set_resources, |
| 469 | .enable_resources = enable_childrens_resources, |
| 470 | .init = 0, |
| 471 | .scan_bus = pci_domain_scan_bus, |
| 472 | }; |
| 473 | |
| 474 | static void cpu_bus_init(device_t dev) |
| 475 | { |
| 476 | initialize_cpus(&dev->link[0]); |
| 477 | } |
| 478 | |
| 479 | static void cpu_bus_noop(device_t dev) |
| 480 | { |
| 481 | } |
| 482 | |
| 483 | static struct device_operations cpu_bus_ops = { |
| 484 | .read_resources = cpu_bus_noop, |
| 485 | .set_resources = cpu_bus_noop, |
| 486 | .enable_resources = cpu_bus_noop, |
| 487 | .init = cpu_bus_init, |
| 488 | .scan_bus = 0, |
| 489 | }; |
| 490 | |
Ronald G. Minnich | 4b8cf1d | 2006-04-10 23:32:23 +0000 | [diff] [blame] | 491 | void chipsetInit (void); |
| 492 | |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 493 | static void enable_dev(struct device *dev) |
| 494 | { |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 495 | printk_debug("gx2 north: enable_dev\n"); |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 496 | void northbridgeinit(void); |
| 497 | void chipsetinit(struct northbridge_amd_gx2_config *nb); |
| 498 | void setup_realmode_idt(void); |
| 499 | void do_vsmbios(void); |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 500 | /* Set the operations if it is a special bus type */ |
| 501 | if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { |
Ronald G. Minnich | 48415d5 | 2006-06-18 01:29:42 +0000 | [diff] [blame] | 502 | struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; |
Ronald G. Minnich | e4ad801 | 2006-03-21 03:38:53 +0000 | [diff] [blame] | 503 | extern void cpubug(void); |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 504 | printk_debug("DEVICE_PATH_PCI_DOMAIN\n"); |
Ronald G. Minnich | e4ad801 | 2006-03-21 03:38:53 +0000 | [diff] [blame] | 505 | /* cpubug MUST be called before setup_gx2(), so we force the issue here */ |
Li-Ta Lo | d8d8fff | 2006-04-13 17:00:38 +0000 | [diff] [blame] | 506 | northbridgeinit(); |
Ronald G. Minnich | e4ad801 | 2006-03-21 03:38:53 +0000 | [diff] [blame] | 507 | cpubug(); |
Ronald G. Minnich | da7ee9f | 2006-07-21 19:21:38 +0000 | [diff] [blame] | 508 | chipsetinit(nb); |
Ronald G. Minnich | d3ba4aa | 2006-05-02 03:07:11 +0000 | [diff] [blame] | 509 | setup_gx2(); |
Ronald G. Minnich | cd6985b | 2006-03-21 23:24:33 +0000 | [diff] [blame] | 510 | /* do this here for now -- this chip really breaks our device model */ |
Li-Ta Lo | 8854d30 | 2006-04-03 22:20:05 +0000 | [diff] [blame] | 511 | setup_realmode_idt(); |
Ronald G. Minnich | cd6985b | 2006-03-21 23:24:33 +0000 | [diff] [blame] | 512 | do_vsmbios(); |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 513 | graphics_init(); |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 514 | dev->ops = &pci_domain_ops; |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 515 | pci_set_method(dev); |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 516 | ram_resource(dev, 0, 0, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE); |
Li-Ta Lo | 8854d30 | 2006-04-03 22:20:05 +0000 | [diff] [blame] | 517 | } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { |
Ronald G. Minnich | 426da0b | 2006-03-15 23:40:30 +0000 | [diff] [blame] | 518 | printk_debug("DEVICE_PATH_APIC_CLUSTER\n"); |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 519 | dev->ops = &cpu_bus_ops; |
| 520 | } |
Ronald G. Minnich | fb93749 | 2006-06-10 22:57:15 +0000 | [diff] [blame] | 521 | printk_debug("gx2 north: end enable_dev\n"); |
Ronald G. Minnich | 2bb216a | 2006-01-27 23:46:30 +0000 | [diff] [blame] | 522 | } |
| 523 | |
| 524 | struct chip_operations northbridge_amd_gx2_ops = { |
| 525 | CHIP_NAME("AMD GX2 Northbridge") |
| 526 | .enable_dev = enable_dev, |
| 527 | }; |