Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 3 | |
| 4 | #include <device/mmio.h> |
| 5 | #include <arch/acpi.h> |
| 6 | #include <console/console.h> |
| 7 | #include <delay.h> |
Felix Held | 00058f5 | 2020-04-06 23:36:24 +0200 | [diff] [blame] | 8 | #include <device/device.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 9 | #include <drivers/i2c/designware/dw_i2c.h> |
| 10 | #include <amdblocks/acpimmio.h> |
| 11 | #include <soc/iomap.h> |
| 12 | #include <soc/pci_devs.h> |
| 13 | #include <soc/southbridge.h> |
| 14 | #include <soc/i2c.h> |
| 15 | #include "chip.h" |
| 16 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 17 | /* Global to provide access to chip.c */ |
| 18 | const char *i2c_acpi_name(const struct device *dev); |
| 19 | |
| 20 | static const uintptr_t i2c_bus_address[] = { |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 21 | APU_I2C2_BASE, |
| 22 | APU_I2C3_BASE, |
| 23 | APU_I2C4_BASE, /* slave device only */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 24 | }; |
| 25 | |
| 26 | uintptr_t dw_i2c_base_address(unsigned int bus) |
| 27 | { |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 28 | if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) |
| 29 | return 0; |
| 30 | |
| 31 | return i2c_bus_address[bus - APU_I2C_MIN_BUS]; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 32 | } |
| 33 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 34 | const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) |
| 35 | { |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 36 | const struct soc_amd_picasso_config *config; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 37 | |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 38 | if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 39 | return NULL; |
| 40 | |
Felix Held | 00058f5 | 2020-04-06 23:36:24 +0200 | [diff] [blame] | 41 | /* config is not NULL; if it was, config_of_soc calls die() internally */ |
| 42 | config = config_of_soc(); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 43 | |
| 44 | return &config->i2c[bus]; |
| 45 | } |
| 46 | |
| 47 | const char *i2c_acpi_name(const struct device *dev) |
| 48 | { |
| 49 | switch (dev->path.mmio.addr) { |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 50 | case APU_I2C2_BASE: |
Marshall Dawson | 59e97b6 | 2019-08-15 17:49:11 -0600 | [diff] [blame] | 51 | return "I2C2"; |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 52 | case APU_I2C3_BASE: |
Marshall Dawson | 59e97b6 | 2019-08-15 17:49:11 -0600 | [diff] [blame] | 53 | return "I2C3"; |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 54 | case APU_I2C4_BASE: |
Marshall Dawson | 59e97b6 | 2019-08-15 17:49:11 -0600 | [diff] [blame] | 55 | return "I2C4"; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 56 | default: |
| 57 | return NULL; |
| 58 | } |
| 59 | } |
| 60 | |
| 61 | int dw_i2c_soc_dev_to_bus(struct device *dev) |
| 62 | { |
| 63 | switch (dev->path.mmio.addr) { |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 64 | case APU_I2C2_BASE: |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 65 | return 2; |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 66 | case APU_I2C3_BASE: |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 67 | return 3; |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 68 | case APU_I2C4_BASE: |
| 69 | return 4; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 70 | } |
| 71 | return -1; |
| 72 | } |
| 73 | |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 74 | __weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } |
| 75 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 76 | static void dw_i2c_soc_init(bool is_early_init) |
| 77 | { |
| 78 | size_t i; |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 79 | const struct soc_amd_picasso_config *config; |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 80 | uint32_t pad_ctrl; |
| 81 | int misc_reg; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 82 | |
Felix Held | 00058f5 | 2020-04-06 23:36:24 +0200 | [diff] [blame] | 83 | /* config is not NULL; if it was, config_of_soc calls die() internally */ |
| 84 | config = config_of_soc(); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 85 | |
| 86 | for (i = 0; i < ARRAY_SIZE(config->i2c); i++) { |
| 87 | const struct dw_i2c_bus_config *cfg = &config->i2c[i]; |
| 88 | |
| 89 | if (cfg->early_init != is_early_init) |
| 90 | continue; |
| 91 | |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 92 | if (dw_i2c_init(i, cfg)) { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 93 | printk(BIOS_ERR, "Failed to init i2c bus %zd\n", i); |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 94 | continue; |
| 95 | } |
| 96 | |
| 97 | misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * i; |
| 98 | pad_ctrl = misc_read32(misc_reg); |
| 99 | |
| 100 | pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; |
| 101 | pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; |
| 102 | |
| 103 | pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; |
| 104 | pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V; |
| 105 | |
| 106 | pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; |
| 107 | pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD |
| 108 | ? I2C_PAD_CTRL_FALLSLEW_STD |
| 109 | : I2C_PAD_CTRL_FALLSLEW_LOW; |
| 110 | pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; |
| 111 | |
| 112 | mainboard_i2c_override(i, &pad_ctrl); |
| 113 | misc_write32(misc_reg, pad_ctrl); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 114 | } |
| 115 | } |
| 116 | |
| 117 | void i2c_soc_early_init(void) |
| 118 | { |
| 119 | dw_i2c_soc_init(true); |
| 120 | } |
| 121 | |
| 122 | void i2c_soc_init(void) |
| 123 | { |
| 124 | dw_i2c_soc_init(false); |
| 125 | } |
| 126 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 127 | struct device_operations picasso_i2c_mmio_ops = { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 128 | /* TODO(teravest): Move I2C resource info here. */ |
| 129 | .read_resources = DEVICE_NOOP, |
| 130 | .set_resources = DEVICE_NOOP, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 131 | .scan_bus = scan_smbus, |
| 132 | .acpi_name = i2c_acpi_name, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 133 | .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | /* |
| 137 | * I2C pins are open drain with external pull up, so in order to bit bang them |
| 138 | * all, SCL pins must become GPIO inputs with no pull, then they need to be |
| 139 | * toggled between input-no-pull and output-low. This table is for the initial |
| 140 | * conversion of all SCL pins to input with no pull. |
| 141 | */ |
| 142 | static const struct soc_amd_gpio i2c_2_gpi[] = { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 143 | PAD_GPI(I2C2_SCL_PIN, PULL_NONE), |
| 144 | PAD_GPI(I2C3_SCL_PIN, PULL_NONE), |
Marshall Dawson | e2c24f7 | 2019-06-20 08:47:58 -0600 | [diff] [blame] | 145 | /* I2C4 is a slave device only */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 146 | }; |
| 147 | #define saved_pins_count ARRAY_SIZE(i2c_2_gpi) |
| 148 | |
| 149 | /* |
| 150 | * To program I2C pins without destroying their programming, the registers |
| 151 | * that will be changed need to be saved first. |
| 152 | */ |
| 153 | static void save_i2c_pin_registers(uint8_t gpio, |
| 154 | struct soc_amd_i2c_save *save_table) |
| 155 | { |
| 156 | uint32_t *gpio_ptr; |
| 157 | |
| 158 | gpio_ptr = (uint32_t *)gpio_get_address(gpio); |
| 159 | save_table->mux_value = iomux_read8(gpio); |
| 160 | save_table->control_value = read32(gpio_ptr); |
| 161 | } |
| 162 | |
| 163 | static void restore_i2c_pin_registers(uint8_t gpio, |
| 164 | struct soc_amd_i2c_save *save_table) |
| 165 | { |
| 166 | uint32_t *gpio_ptr; |
| 167 | |
| 168 | gpio_ptr = (uint32_t *)gpio_get_address(gpio); |
| 169 | iomux_write8(gpio, save_table->mux_value); |
| 170 | iomux_read8(gpio); |
| 171 | write32(gpio_ptr, save_table->control_value); |
| 172 | read32(gpio_ptr); |
| 173 | } |
| 174 | |
| 175 | /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ |
| 176 | void sb_reset_i2c_slaves(void) |
| 177 | { |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 178 | const struct soc_amd_picasso_config *cfg; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 179 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
| 180 | struct soc_amd_i2c_save save_table[saved_pins_count]; |
| 181 | uint8_t i, j, control; |
| 182 | |
| 183 | if (!dev || !dev->chip_info) |
| 184 | return; |
| 185 | cfg = dev->chip_info; |
| 186 | control = cfg->i2c_scl_reset & GPIO_I2C_MASK; |
| 187 | if (control == 0) |
| 188 | return; |
| 189 | |
| 190 | /* Save and reprogram I2C SCL pins */ |
| 191 | for (i = 0; i < saved_pins_count; i++) |
| 192 | save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); |
| 193 | program_gpios(i2c_2_gpi, saved_pins_count); |
| 194 | |
| 195 | /* |
| 196 | * Toggle SCL back and forth 9 times under 100KHz. A single read is |
| 197 | * needed after the writes to force the posted write to complete. |
| 198 | */ |
| 199 | for (j = 0; j < 9; j++) { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 200 | if (control & GPIO_I2C2_SCL) |
| 201 | write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); |
| 202 | if (control & GPIO_I2C3_SCL) |
| 203 | write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); |
| 204 | |
| 205 | read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ |
| 206 | udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ |
| 207 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 208 | if (control & GPIO_I2C2_SCL) |
| 209 | write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); |
| 210 | if (control & GPIO_I2C3_SCL) |
| 211 | write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); |
| 212 | |
| 213 | read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ |
| 214 | udelay(4); |
| 215 | } |
| 216 | |
| 217 | /* Restore I2C pins. */ |
| 218 | for (i = 0; i < saved_pins_count; i++) |
| 219 | restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); |
| 220 | } |