Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Google |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <device/mmio.h> |
| 17 | #include <arch/acpi.h> |
| 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
| 20 | #include <drivers/i2c/designware/dw_i2c.h> |
| 21 | #include <amdblocks/acpimmio.h> |
| 22 | #include <soc/iomap.h> |
| 23 | #include <soc/pci_devs.h> |
| 24 | #include <soc/southbridge.h> |
| 25 | #include <soc/i2c.h> |
| 26 | #include "chip.h" |
| 27 | |
| 28 | #define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) |
| 29 | #define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) |
| 30 | #define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) |
| 31 | #define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2)) |
| 32 | #define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3)) |
| 33 | |
| 34 | /* Global to provide access to chip.c */ |
| 35 | const char *i2c_acpi_name(const struct device *dev); |
| 36 | |
| 37 | static const uintptr_t i2c_bus_address[] = { |
| 38 | I2CA_BASE_ADDRESS, |
| 39 | I2CB_BASE_ADDRESS, |
| 40 | I2CC_BASE_ADDRESS, |
| 41 | I2CD_BASE_ADDRESS, |
| 42 | }; |
| 43 | |
| 44 | uintptr_t dw_i2c_base_address(unsigned int bus) |
| 45 | { |
| 46 | return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; |
| 47 | } |
| 48 | |
| 49 | static const struct soc_amd_stoneyridge_config *get_soc_config(void) |
| 50 | { |
| 51 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
| 52 | |
| 53 | if (!dev || !dev->chip_info) { |
| 54 | printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", |
| 55 | __func__); |
| 56 | return NULL; |
| 57 | } |
| 58 | |
| 59 | return dev->chip_info; |
| 60 | } |
| 61 | |
| 62 | const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) |
| 63 | { |
| 64 | const struct soc_amd_stoneyridge_config *config; |
| 65 | |
| 66 | if (bus >= ARRAY_SIZE(i2c_bus_address)) |
| 67 | return NULL; |
| 68 | |
| 69 | config = get_soc_config(); |
| 70 | if (config == NULL) |
| 71 | return NULL; |
| 72 | |
| 73 | return &config->i2c[bus]; |
| 74 | } |
| 75 | |
| 76 | const char *i2c_acpi_name(const struct device *dev) |
| 77 | { |
| 78 | switch (dev->path.mmio.addr) { |
| 79 | case I2CA_BASE_ADDRESS: |
| 80 | return "I2CA"; |
| 81 | case I2CB_BASE_ADDRESS: |
| 82 | return "I2CB"; |
| 83 | case I2CC_BASE_ADDRESS: |
| 84 | return "I2CC"; |
| 85 | case I2CD_BASE_ADDRESS: |
| 86 | return "I2CD"; |
| 87 | default: |
| 88 | return NULL; |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | int dw_i2c_soc_dev_to_bus(struct device *dev) |
| 93 | { |
| 94 | switch (dev->path.mmio.addr) { |
| 95 | case I2CA_BASE_ADDRESS: |
| 96 | return 0; |
| 97 | case I2CB_BASE_ADDRESS: |
| 98 | return 1; |
| 99 | case I2CC_BASE_ADDRESS: |
| 100 | return 2; |
| 101 | case I2CD_BASE_ADDRESS: |
| 102 | return 3; |
| 103 | } |
| 104 | return -1; |
| 105 | } |
| 106 | |
| 107 | static void dw_i2c_soc_init(bool is_early_init) |
| 108 | { |
| 109 | size_t i; |
| 110 | const struct soc_amd_stoneyridge_config *config; |
| 111 | |
| 112 | config = get_soc_config(); |
| 113 | |
| 114 | if (config == NULL) |
| 115 | return; |
| 116 | |
| 117 | for (i = 0; i < ARRAY_SIZE(config->i2c); i++) { |
| 118 | const struct dw_i2c_bus_config *cfg = &config->i2c[i]; |
| 119 | |
| 120 | if (cfg->early_init != is_early_init) |
| 121 | continue; |
| 122 | |
| 123 | if (dw_i2c_init(i, cfg)) |
| 124 | printk(BIOS_ERR, "Failed to init i2c bus %zd\n", i); |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | void i2c_soc_early_init(void) |
| 129 | { |
| 130 | dw_i2c_soc_init(true); |
| 131 | } |
| 132 | |
| 133 | void i2c_soc_init(void) |
| 134 | { |
| 135 | dw_i2c_soc_init(false); |
| 136 | } |
| 137 | |
| 138 | struct device_operations stoneyridge_i2c_mmio_ops = { |
| 139 | /* TODO(teravest): Move I2C resource info here. */ |
| 140 | .read_resources = DEVICE_NOOP, |
| 141 | .set_resources = DEVICE_NOOP, |
| 142 | .enable_resources = DEVICE_NOOP, |
| 143 | .scan_bus = scan_smbus, |
| 144 | .acpi_name = i2c_acpi_name, |
| 145 | .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, |
| 146 | }; |
| 147 | |
| 148 | /* |
| 149 | * I2C pins are open drain with external pull up, so in order to bit bang them |
| 150 | * all, SCL pins must become GPIO inputs with no pull, then they need to be |
| 151 | * toggled between input-no-pull and output-low. This table is for the initial |
| 152 | * conversion of all SCL pins to input with no pull. |
| 153 | */ |
| 154 | static const struct soc_amd_gpio i2c_2_gpi[] = { |
| 155 | PAD_GPI(I2C0_SCL_PIN, PULL_NONE), |
| 156 | PAD_GPI(I2C1_SCL_PIN, PULL_NONE), |
| 157 | PAD_GPI(I2C2_SCL_PIN, PULL_NONE), |
| 158 | PAD_GPI(I2C3_SCL_PIN, PULL_NONE), |
| 159 | }; |
| 160 | #define saved_pins_count ARRAY_SIZE(i2c_2_gpi) |
| 161 | |
| 162 | /* |
| 163 | * To program I2C pins without destroying their programming, the registers |
| 164 | * that will be changed need to be saved first. |
| 165 | */ |
| 166 | static void save_i2c_pin_registers(uint8_t gpio, |
| 167 | struct soc_amd_i2c_save *save_table) |
| 168 | { |
| 169 | uint32_t *gpio_ptr; |
| 170 | |
| 171 | gpio_ptr = (uint32_t *)gpio_get_address(gpio); |
| 172 | save_table->mux_value = iomux_read8(gpio); |
| 173 | save_table->control_value = read32(gpio_ptr); |
| 174 | } |
| 175 | |
| 176 | static void restore_i2c_pin_registers(uint8_t gpio, |
| 177 | struct soc_amd_i2c_save *save_table) |
| 178 | { |
| 179 | uint32_t *gpio_ptr; |
| 180 | |
| 181 | gpio_ptr = (uint32_t *)gpio_get_address(gpio); |
| 182 | iomux_write8(gpio, save_table->mux_value); |
| 183 | iomux_read8(gpio); |
| 184 | write32(gpio_ptr, save_table->control_value); |
| 185 | read32(gpio_ptr); |
| 186 | } |
| 187 | |
| 188 | /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ |
| 189 | void sb_reset_i2c_slaves(void) |
| 190 | { |
| 191 | const struct soc_amd_stoneyridge_config *cfg; |
| 192 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
| 193 | struct soc_amd_i2c_save save_table[saved_pins_count]; |
| 194 | uint8_t i, j, control; |
| 195 | |
| 196 | if (!dev || !dev->chip_info) |
| 197 | return; |
| 198 | cfg = dev->chip_info; |
| 199 | control = cfg->i2c_scl_reset & GPIO_I2C_MASK; |
| 200 | if (control == 0) |
| 201 | return; |
| 202 | |
| 203 | /* Save and reprogram I2C SCL pins */ |
| 204 | for (i = 0; i < saved_pins_count; i++) |
| 205 | save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); |
| 206 | program_gpios(i2c_2_gpi, saved_pins_count); |
| 207 | |
| 208 | /* |
| 209 | * Toggle SCL back and forth 9 times under 100KHz. A single read is |
| 210 | * needed after the writes to force the posted write to complete. |
| 211 | */ |
| 212 | for (j = 0; j < 9; j++) { |
| 213 | if (control & GPIO_I2C0_SCL) |
| 214 | write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); |
| 215 | if (control & GPIO_I2C1_SCL) |
| 216 | write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); |
| 217 | if (control & GPIO_I2C2_SCL) |
| 218 | write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); |
| 219 | if (control & GPIO_I2C3_SCL) |
| 220 | write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); |
| 221 | |
| 222 | read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ |
| 223 | udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ |
| 224 | |
| 225 | if (control & GPIO_I2C0_SCL) |
| 226 | write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); |
| 227 | if (control & GPIO_I2C1_SCL) |
| 228 | write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); |
| 229 | if (control & GPIO_I2C2_SCL) |
| 230 | write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); |
| 231 | if (control & GPIO_I2C3_SCL) |
| 232 | write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); |
| 233 | |
| 234 | read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ |
| 235 | udelay(4); |
| 236 | } |
| 237 | |
| 238 | /* Restore I2C pins. */ |
| 239 | for (i = 0; i < saved_pins_count; i++) |
| 240 | restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); |
| 241 | } |