Angel Pons | 8a3453f | 2020-04-02 23:48:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
| 5 | #include <delay.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/smbus.h> |
| 8 | #include <device/pci.h> |
| 9 | #include "chip.h" |
| 10 | |
| 11 | /* Chip commands */ |
| 12 | #define RTD2132_COMMAND 0x01 |
| 13 | #define RTD2132_DATA 0x00 |
| 14 | #define RTD2132_FIRMWARE 0x80 |
| 15 | #define RTD2132_FIRMWARE_START 0x00 |
| 16 | #define RTD2132_FIRMWARE_STOP 0x01 |
| 17 | |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 18 | /* Panel Power Sequence Timing Registers. */ |
| 19 | #define RTD2132_COMMAND_PWR_SEQ_T1 0x32 /* 1ms units. */ |
| 20 | #define RTD2132_COMMAND_PWR_SEQ_T2 0x33 /* 4ms units. */ |
| 21 | #define RTD2132_COMMAND_PWR_SEQ_T3 0x34 /* 1ms units. */ |
| 22 | #define RTD2132_COMMAND_PWR_SEQ_T4 0x35 /* 1ms units. */ |
| 23 | #define RTD2132_COMMAND_PWR_SEQ_T5 0x36 /* 4ms units. */ |
| 24 | #define RTD2132_COMMAND_PWR_SEQ_T6 0x37 /* 1ms units. */ |
| 25 | #define RTD2132_COMMAND_PWR_SEQ_T7 0x38 /* 4ms units. */ |
| 26 | |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 27 | /* Spread spectrum configuration */ |
| 28 | #define RTD2132_COMMAND_SSCG_CONFIG_0 0x39 |
| 29 | #define RTD2132_SSCG_ENABLE 0xa0 |
| 30 | #define RTD2132_SSCG_DISABLE 0x20 |
| 31 | #define RTD2132_COMMAND_SSCG_CONFIG_1 0x3a |
| 32 | #define RTD2132_SSCG_CONFIG_DISABLED 0x01 /* DISABLED */ |
| 33 | #define RTD2132_SSCG_CONFIG_0_5 0x07 /* 0.5% */ |
| 34 | #define RTD2132_SSCG_CONFIG_1_0 0x0f /* 1.0% */ |
| 35 | #define RTD2132_SSCG_CONFIG_1_5 0x16 /* 1.5% */ |
| 36 | |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 37 | /* LVDS Swap */ |
| 38 | #define RTD2132_COMMAND_LVDS_SWAP 0x3b |
| 39 | #define RTD2132_LVDS_SWAP_DUAL 0x80 |
| 40 | #define RTD2132_LVDS_SWAP_NORMAL 0x04 |
| 41 | #define RTD2132_LVDS_SWAP_MIRROR 0x14 |
| 42 | #define RTD2132_LVDS_SWAP_P_N 0x24 |
| 43 | #define RTD2132_LVDS_SWAP_MIRROR_P_N 0x34 |
| 44 | #define RTD2132_LVDS_SWAP_R_L 0x0c |
| 45 | |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 46 | /* Configuration values from devicetree */ |
| 47 | #define RTD2132_SSCG_PERCENT_0_0 0x00 /* DISABLED */ |
| 48 | #define RTD2132_SSCG_PERCENT_0_5 0x05 /* 0.5% */ |
| 49 | #define RTD2132_SSCG_PERCENT_1_0 0x10 /* 1.0% */ |
| 50 | #define RTD2132_SSCG_PERCENT_1_5 0x15 /* 1.5% */ |
| 51 | |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 52 | #define RTD2132_LVDS_SWAP_CFG_DUAL 0x80 |
| 53 | #define RTD2132_LVDS_SWAP_CFG_NORMAL 0x00 |
| 54 | #define RTD2132_LVDS_SWAP_CFG_MIRROR 0x01 |
| 55 | #define RTD2132_LVDS_SWAP_CFG_P_N 0x02 |
| 56 | #define RTD2132_LVDS_SWAP_CFG_MIRROR_P_N 0x03 |
| 57 | #define RTD2132_LVDS_SWAP_CFG_R_L 0x04 |
| 58 | |
| 59 | #define RTD2132_DEBUG_REG 0 |
| 60 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 61 | static void rtd2132_write_reg(struct device *dev, u8 reg, u8 value) |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 62 | { |
| 63 | if (RTD2132_DEBUG_REG) |
| 64 | printk(BIOS_DEBUG, "RTD2132 0x%02x <- 0x%02x\n", reg, value); |
| 65 | smbus_write_byte(dev, RTD2132_COMMAND, reg); |
| 66 | smbus_write_byte(dev, RTD2132_DATA, value); |
| 67 | } |
| 68 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 69 | static void rtd2132_firmware_stop(struct device *dev) |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 70 | { |
| 71 | smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_STOP); |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 72 | mdelay(60); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 73 | } |
| 74 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 75 | static void rtd2132_firmware_start(struct device *dev) |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 76 | { |
| 77 | smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_START); |
| 78 | } |
| 79 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 80 | static void rtd2132_pps(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 81 | { |
| 82 | /* T2, T5, and T7 register values are in units of 4ms. */ |
| 83 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T1, cfg->t1); |
| 84 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T2, cfg->t2 / 4); |
| 85 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T3, cfg->t3); |
| 86 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T4, cfg->t4); |
| 87 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T5, cfg->t5 / 4); |
| 88 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T6, cfg->t6); |
| 89 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T7, cfg->t7 / 4); |
| 90 | } |
| 91 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 92 | static void rtd2132_sscg_enable(struct device *dev, u8 sscg_percent) |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 93 | { |
| 94 | /* SSCG_Config_0 */ |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 95 | rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, |
| 96 | RTD2132_SSCG_ENABLE); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 97 | |
| 98 | /* SSCG_Config_1 */ |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 99 | rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_1, sscg_percent); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 100 | } |
| 101 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 102 | static void rtd2132_sscg_disable(struct device *dev) |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 103 | { |
| 104 | /* SSCG_Config_0 */ |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 105 | rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, |
| 106 | RTD2132_SSCG_DISABLE); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 107 | |
| 108 | /* SSCG_Config_1 */ |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 109 | rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_1, |
| 110 | RTD2132_SSCG_CONFIG_DISABLED); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 111 | } |
| 112 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 113 | static void rtd2132_sscg(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 114 | { |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 115 | switch (cfg->sscg_percent) { |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 116 | case RTD2132_SSCG_PERCENT_0_0: |
| 117 | printk(BIOS_INFO, "RTD2132: Disable Spread Spectrum\n"); |
| 118 | rtd2132_sscg_disable(dev); |
| 119 | break; |
| 120 | case RTD2132_SSCG_PERCENT_0_5: |
| 121 | printk(BIOS_INFO, "RTD2132: Enable 0.5%% Spread Spectrum\n"); |
| 122 | rtd2132_sscg_enable(dev, RTD2132_SSCG_CONFIG_0_5); |
| 123 | break; |
| 124 | case RTD2132_SSCG_PERCENT_1_0: |
| 125 | printk(BIOS_INFO, "RTD2132: Enable 1.0%% Spread Spectrum\n"); |
| 126 | rtd2132_sscg_enable(dev, RTD2132_SSCG_CONFIG_1_0); |
| 127 | break; |
| 128 | case RTD2132_SSCG_PERCENT_1_5: |
| 129 | printk(BIOS_INFO, "RTD2132: Enable 1.5%% Spread Spectrum\n"); |
| 130 | rtd2132_sscg_enable(dev, RTD2132_SSCG_CONFIG_1_5); |
| 131 | break; |
| 132 | default: |
| 133 | printk(BIOS_ERR, "RTD2132: Invalid Spread Spectrum 0x%02x\n", |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 134 | cfg->sscg_percent); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 135 | } |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 136 | } |
| 137 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 138 | static void rtd2132_lvds_swap(struct device *dev, |
Martin Roth | b9810a4 | 2017-07-23 20:00:04 -0600 | [diff] [blame] | 139 | struct drivers_i2c_rtd2132_config *cfg) |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 140 | { |
| 141 | u8 swap_value = RTD2132_LVDS_SWAP_NORMAL; |
| 142 | |
| 143 | switch (cfg->lvds_swap & ~RTD2132_LVDS_SWAP_CFG_DUAL) { |
| 144 | case RTD2132_LVDS_SWAP_CFG_NORMAL: |
| 145 | swap_value = RTD2132_LVDS_SWAP_NORMAL; |
| 146 | break; |
| 147 | case RTD2132_LVDS_SWAP_CFG_MIRROR: |
| 148 | swap_value = RTD2132_LVDS_SWAP_MIRROR; |
| 149 | break; |
| 150 | case RTD2132_LVDS_SWAP_CFG_P_N: |
| 151 | swap_value = RTD2132_LVDS_SWAP_P_N; |
| 152 | break; |
| 153 | case RTD2132_LVDS_SWAP_CFG_MIRROR_P_N: |
| 154 | swap_value = RTD2132_LVDS_SWAP_MIRROR_P_N; |
| 155 | break; |
| 156 | case RTD2132_LVDS_SWAP_CFG_R_L: |
| 157 | swap_value = RTD2132_LVDS_SWAP_R_L; |
| 158 | break; |
| 159 | default: |
| 160 | printk(BIOS_ERR, "RTD2132: Invalid LVDS swap value 0x%02x\n", |
| 161 | cfg->lvds_swap); |
| 162 | } |
| 163 | |
| 164 | if (cfg->lvds_swap & RTD2132_LVDS_SWAP_CFG_DUAL) |
| 165 | swap_value |= RTD2132_LVDS_SWAP_DUAL; |
| 166 | |
Idwer Vollering | d26da9c | 2013-12-22 21:38:18 +0000 | [diff] [blame] | 167 | printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value); |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 168 | |
| 169 | rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); |
| 170 | } |
| 171 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 172 | static void rtd2132_defaults(struct device *dev) |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 173 | { |
| 174 | static const struct def_setting { |
| 175 | u8 reg; |
| 176 | u8 value; |
| 177 | } def_settings[] = { |
| 178 | { 0x3c, 0x06 }, |
| 179 | { 0x3d, 0x38 }, |
| 180 | { 0x3e, 0x73 }, |
| 181 | { 0x3f, 0x33 }, |
| 182 | { 0x06, 0x90 }, |
| 183 | { 0x06, 0xb0 }, |
| 184 | { 0x06, 0x80 }, |
| 185 | }; |
| 186 | int i; |
| 187 | |
| 188 | for (i = 0; i < ARRAY_SIZE(def_settings); i++) |
| 189 | rtd2132_write_reg(dev, def_settings[i].reg, |
| 190 | def_settings[i].value); |
| 191 | } |
| 192 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 193 | static void rtd2132_setup(struct device *dev) |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 194 | { |
| 195 | struct drivers_i2c_rtd2132_config *config = dev->chip_info; |
| 196 | |
| 197 | if (!config) |
| 198 | return; |
| 199 | |
| 200 | /* Stop running firmware */ |
| 201 | rtd2132_firmware_stop(dev); |
| 202 | |
| 203 | /* Panel Power Sequencing Settings. */ |
| 204 | rtd2132_pps(dev, config); |
| 205 | |
| 206 | /* Spread spectrum configuration */ |
| 207 | rtd2132_sscg(dev, config); |
| 208 | |
| 209 | /* LVDS Swap Setting. */ |
| 210 | rtd2132_lvds_swap(dev, config); |
| 211 | |
| 212 | /* Default settings. */ |
| 213 | rtd2132_defaults(dev); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 214 | |
| 215 | /* Start firmware */ |
| 216 | rtd2132_firmware_start(dev); |
| 217 | } |
| 218 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 219 | static void rtd2132_init(struct device *dev) |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 220 | { |
| 221 | if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && |
| 222 | ops_smbus_bus(get_pbus_smbus(dev))) { |
| 223 | rtd2132_setup(dev); |
| 224 | } |
| 225 | } |
| 226 | |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 227 | static struct device_operations rtd2132_operations = { |
Edward O'Callaghan | 524625d | 2014-10-31 07:55:45 +1100 | [diff] [blame] | 228 | .read_resources = DEVICE_NOOP, |
| 229 | .set_resources = DEVICE_NOOP, |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 230 | .init = rtd2132_init, |
| 231 | }; |
| 232 | |
| 233 | static void enable_dev(struct device *dev) |
| 234 | { |
| 235 | dev->ops = &rtd2132_operations; |
| 236 | } |
| 237 | |
| 238 | struct chip_operations drivers_i2c_rtd2132_ops = { |
| 239 | CHIP_NAME("Realtek RTD2132 LVDS Bridge") |
| 240 | .enable_dev = enable_dev, |
| 241 | }; |