Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <stddef.h> |
| 21 | #include <arch/io.h> |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 22 | #include <bootmode.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 23 | #include <cbfs.h> |
| 24 | #include <cbmem.h> |
| 25 | #include <console/console.h> |
| 26 | #include <device/pci_def.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 27 | #include <halt.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 28 | #include <baytrail/gpio.h> |
Duncan Laurie | d8c4f2b | 2014-04-22 10:46:06 -0700 | [diff] [blame] | 29 | #include <soc/intel/common/mrc_cache.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 30 | #include <baytrail/iomap.h> |
Aaron Durbin | 3ccb3ce | 2013-10-11 00:26:04 -0500 | [diff] [blame] | 31 | #include <baytrail/iosf.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 32 | #include <baytrail/pci_devs.h> |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 33 | #include <baytrail/reset.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 34 | #include <baytrail/romstage.h> |
Aaron Durbin | 107b71c | 2014-01-09 14:35:41 -0600 | [diff] [blame] | 35 | #include <ec/google/chromeec/ec.h> |
| 36 | #include <ec/google/chromeec/ec_commands.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 37 | |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 38 | static void reset_system(void) |
| 39 | { |
| 40 | warm_reset(); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 41 | halt(); |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 42 | } |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 43 | |
| 44 | static void enable_smbus(void) |
| 45 | { |
| 46 | uint32_t reg; |
| 47 | const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); |
| 48 | |
| 49 | /* SMBus I/O BAR */ |
| 50 | reg = SMBUS_BASE_ADDRESS | 2; |
| 51 | pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); |
| 52 | /* Enable decode of I/O space. */ |
| 53 | reg = pci_read_config16(smbus_dev, PCI_COMMAND); |
| 54 | reg |= 0x1; |
| 55 | pci_write_config16(smbus_dev, PCI_COMMAND, reg); |
| 56 | /* Enable Host Controller */ |
| 57 | reg = pci_read_config8(smbus_dev, 0x40); |
| 58 | reg |= 1; |
| 59 | pci_write_config8(smbus_dev, 0x40, reg); |
| 60 | |
| 61 | /* Configure pads to be used for SMBus */ |
| 62 | score_select_func(PCU_SMB_CLK_PAD, 1); |
| 63 | score_select_func(PCU_SMB_DATA_PAD, 1); |
| 64 | } |
| 65 | |
Aaron Durbin | 833ff35 | 2013-10-02 11:06:31 -0500 | [diff] [blame] | 66 | static void ABI_X86 send_to_console(unsigned char b) |
| 67 | { |
Kyösti Mälkki | 657e0be | 2014-02-04 19:03:57 +0200 | [diff] [blame] | 68 | do_putchar(b); |
Aaron Durbin | 833ff35 | 2013-10-02 11:06:31 -0500 | [diff] [blame] | 69 | } |
| 70 | |
Aaron Durbin | 3ccb3ce | 2013-10-11 00:26:04 -0500 | [diff] [blame] | 71 | static void print_dram_info(void) |
| 72 | { |
| 73 | const int mrc_ver_reg = 0xf0; |
| 74 | const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); |
| 75 | uint32_t reg; |
| 76 | int num_channels; |
| 77 | int speed; |
| 78 | uint32_t ch0; |
| 79 | uint32_t ch1; |
| 80 | |
| 81 | reg = pci_read_config32(soc_dev, mrc_ver_reg); |
| 82 | |
| 83 | printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); |
| 84 | |
| 85 | /* Number of channels enabled and DDR3 type. Determine number of |
| 86 | * channels by keying of the rank enable bits [3:0]. * */ |
| 87 | ch0 = iosf_dunit_ch0_read(DRP); |
| 88 | ch1 = iosf_dunit_ch1_read(DRP); |
| 89 | num_channels = 0; |
| 90 | if (ch0 & DRP_RANK_MASK) |
| 91 | num_channels++; |
| 92 | if (ch1 & DRP_RANK_MASK) |
| 93 | num_channels++; |
| 94 | |
| 95 | printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, |
| 96 | (reg & (1 << 22)) ? "LP" : ""); |
| 97 | |
| 98 | /* DRAM frequency -- all channels run at same frequency. */ |
| 99 | reg = iosf_dunit_read(DTR0); |
| 100 | switch (reg & 0x3) { |
| 101 | case 0: |
| 102 | speed = 800; break; |
| 103 | case 1: |
| 104 | speed = 1066; break; |
| 105 | case 2: |
| 106 | speed = 1333; break; |
| 107 | case 3: |
| 108 | speed = 1600; break; |
| 109 | } |
| 110 | printk(BIOS_INFO, "%dMHz\n", speed); |
| 111 | } |
| 112 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 113 | void raminit(struct mrc_params *mp, int prev_sleep_state) |
| 114 | { |
| 115 | int ret; |
| 116 | mrc_wrapper_entry_t mrc_entry; |
| 117 | const struct mrc_saved_data *cache; |
| 118 | |
| 119 | /* Fill in default entries. */ |
| 120 | mp->version = MRC_PARAMS_VER; |
Aaron Durbin | 833ff35 | 2013-10-02 11:06:31 -0500 | [diff] [blame] | 121 | mp->console_out = &send_to_console; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 122 | mp->prev_sleep_state = prev_sleep_state; |
Patrick Georgi | 5b33dc1 | 2014-05-07 20:20:10 +0200 | [diff] [blame] | 123 | mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 124 | |
| 125 | /* Default to 2GiB IO hole. */ |
| 126 | if (!mp->io_hole_mb) |
| 127 | mp->io_hole_mb = 2048; |
| 128 | |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 129 | if (recovery_mode_enabled()) { |
| 130 | printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); |
| 131 | } else if (!mrc_cache_get_current(&cache)) { |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 132 | mp->saved_data_size = cache->size; |
| 133 | mp->saved_data = &cache->data[0]; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 134 | } else if (prev_sleep_state == 3) { |
| 135 | /* If waking from S3 and no cache then. */ |
| 136 | printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); |
| 137 | post_code(POST_RESUME_FAILURE); |
| 138 | reset_system(); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 139 | } else { |
| 140 | printk(BIOS_DEBUG, "No MRC cache found.\n"); |
Aaron Durbin | 107b71c | 2014-01-09 14:35:41 -0600 | [diff] [blame] | 141 | #if CONFIG_EC_GOOGLE_CHROMEEC |
| 142 | if (prev_sleep_state == 0) { |
| 143 | /* Ensure EC is running RO firmware. */ |
| 144 | google_chromeec_check_ec_image(EC_IMAGE_RO); |
| 145 | } |
| 146 | #endif |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 147 | } |
| 148 | |
Aaron Durbin | 1131889 | 2014-04-02 20:46:13 -0500 | [diff] [blame] | 149 | /* Determine if mrc.bin is in the cbfs. */ |
Aaron Durbin | a30f7e6 | 2015-03-31 20:33:53 -0500 | [diff] [blame^] | 150 | if (cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, |
| 151 | NULL) == NULL) { |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 152 | printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); |
| 153 | return; |
| 154 | } |
Aaron Durbin | 1131889 | 2014-04-02 20:46:13 -0500 | [diff] [blame] | 155 | |
| 156 | /* |
| 157 | * The entry point is currently the first instruction. Handle the |
| 158 | * case of an ELF file being put in the cbfs by setting the entry |
| 159 | * to the CONFIG_MRC_BIN_ADDRESS. |
| 160 | */ |
| 161 | mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; |
| 162 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 163 | if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) |
| 164 | enable_smbus(); |
| 165 | |
| 166 | ret = mrc_entry(mp); |
| 167 | |
Aaron Durbin | 3ccb3ce | 2013-10-11 00:26:04 -0500 | [diff] [blame] | 168 | print_dram_info(); |
| 169 | |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 170 | if (prev_sleep_state != 3) { |
| 171 | cbmem_initialize_empty(); |
| 172 | } else if (cbmem_initialize()) { |
| 173 | #if CONFIG_HAVE_ACPI_RESUME |
| 174 | printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); |
| 175 | /* Failed S3 resume, reset to come up cleanly */ |
| 176 | reset_system(); |
| 177 | #endif |
| 178 | } |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 179 | |
| 180 | printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); |
| 181 | printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, |
| 182 | mp->data_to_save_size); |
| 183 | |
| 184 | if (mp->data_to_save != NULL && mp->data_to_save_size > 0) |
| 185 | mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size); |
| 186 | } |