Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 2 | |
| 3 | #ifndef SOC_INTEL_COMMON_CSE_H |
| 4 | #define SOC_INTEL_COMMON_CSE_H |
| 5 | |
Bora Guvendik | 9405049 | 2023-03-12 12:24:58 -0700 | [diff] [blame] | 6 | #include <intelblocks/cse_telemetry.h> |
Rizwan Qureshi | b8b8ec8 | 2020-03-30 16:52:19 +0530 | [diff] [blame] | 7 | #include <types.h> |
V Sowmya | 338b83c | 2020-11-11 07:04:13 +0530 | [diff] [blame] | 8 | #include <vb2_api.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 9 | |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 10 | /* MKHI Command groups */ |
Sridhar Siricilla | e9f4e56 | 2023-05-05 10:50:43 +0530 | [diff] [blame] | 11 | enum mkhi_group_id { |
| 12 | MKHI_GROUP_ID_CBM = 0x0, |
| 13 | MKHI_GROUP_ID_HMRFPO = 0x5, |
| 14 | MKHI_GROUP_ID_GEN = 0xff, |
| 15 | MKHI_GROUP_ID_BUP_COMMON = 0xf0, |
| 16 | MKHI_GROUP_ID_FWCAPS = 0x3, |
| 17 | }; |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 18 | |
| 19 | /* Global Reset Command ID */ |
Sridhar Siricilla | 1d20cfa | 2020-01-12 12:29:15 +0530 | [diff] [blame] | 20 | #define MKHI_CBM_GLOBAL_RESET_REQ 0xb |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 21 | |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 22 | /* Set State Command ID */ |
| 23 | #define MKHI_SET_ME_DISABLE 0x3 |
| 24 | #define MKHI_SET_ME_ENABLE 0x3 |
| 25 | |
Sridhar Siricilla | 83af733 | 2020-01-08 00:13:21 +0530 | [diff] [blame] | 26 | /* Origin of Global Reset command */ |
Sridhar Siricilla | 1d20cfa | 2020-01-12 12:29:15 +0530 | [diff] [blame] | 27 | #define GR_ORIGIN_BIOS_POST 0x2 |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 28 | |
| 29 | /* HMRFPO Command Ids */ |
Sridhar Siricilla | 1d20cfa | 2020-01-12 12:29:15 +0530 | [diff] [blame] | 30 | #define MKHI_HMRFPO_ENABLE 0x1 |
| 31 | #define MKHI_HMRFPO_GET_STATUS 0x3 |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 32 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 33 | /* Get Firmware Version Command Id */ |
| 34 | #define MKHI_GEN_GET_FW_VERSION 0x2 |
| 35 | |
Michał Żygowski | daa1710 | 2022-10-04 10:55:38 +0200 | [diff] [blame] | 36 | /* Firmware Feature Shipment Time State Override Command Id */ |
| 37 | #define MKHI_GEN_FW_FEATURE_SHIPMENT_OVER 0x14 |
| 38 | #define ME_FW_FEATURE_PTT BIT(29) |
| 39 | |
| 40 | /* Get Firmware Feature State Command Id */ |
| 41 | #define MKHI_FWCAPS_GET_FW_FEATURE_STATE 0x02 |
| 42 | #define ME_FEATURE_STATE_RULE_ID 0x20 |
Anil Kumar | a2d10bb | 2023-05-01 11:44:47 -0700 | [diff] [blame^] | 43 | #define ME_FW_FEATURE_PSR BIT(5) |
Tim Wawrzynczak | 9fdd2b2 | 2021-06-18 10:34:09 -0600 | [diff] [blame] | 44 | /* MEI bus disable command. Must be sent to MEI client endpoint, not MKHI */ |
| 45 | #define MEI_BUS_DISABLE_COMMAND 0xc |
| 46 | |
Tim Wawrzynczak | 064ca18 | 2021-06-17 12:40:13 -0600 | [diff] [blame] | 47 | /* Set End-of-POST in CSE */ |
| 48 | #define MKHI_END_OF_POST 0xc |
| 49 | |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 50 | /* Boot partition info and set boot partition info command ids */ |
| 51 | #define MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO 0x1c |
| 52 | #define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO 0x1d |
Sridhar Siricilla | 2f6d555 | 2020-04-19 23:39:02 +0530 | [diff] [blame] | 53 | #define MKHI_BUP_COMMON_DATA_CLEAR 0x20 |
Dinesh Gehlot | f963feb | 2023-03-24 06:39:33 +0000 | [diff] [blame] | 54 | #define GEN_GET_IMAGE_FW_VERSION 0x1c |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 55 | |
Bora Guvendik | f33c9bf | 2021-11-05 23:09:25 -0700 | [diff] [blame] | 56 | /* Get boot performance command id */ |
| 57 | #define MKHI_BUP_COMMON_GET_BOOT_PERF_DATA 0x8 |
| 58 | |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 59 | /* ME Current Working States */ |
Sridhar Siricilla | 1d20cfa | 2020-01-12 12:29:15 +0530 | [diff] [blame] | 60 | #define ME_HFS1_CWS_NORMAL 0x5 |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 61 | |
| 62 | /* ME Current Operation Modes */ |
Sridhar Siricilla | 1d20cfa | 2020-01-12 12:29:15 +0530 | [diff] [blame] | 63 | #define ME_HFS1_COM_NORMAL 0x0 |
| 64 | #define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 |
| 65 | #define ME_HFS1_COM_SECOVER_MEI_MSG 0x5 |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 66 | |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 67 | /* ME Disable Rule */ |
| 68 | #define ME_DISABLE_RULE_ID 6 |
| 69 | #define ME_DISABLE_RULE_LENGTH 4 |
| 70 | #define ME_DISABLE_COMMAND 0 |
| 71 | #define ME_DISABLE_ATTEMPTS 3 |
| 72 | |
Sridhar Siricilla | 3d27705 | 2020-02-06 14:21:49 +0530 | [diff] [blame] | 73 | /* ME Firmware SKU Types */ |
Sridhar Siricilla | e9f4e56 | 2023-05-05 10:50:43 +0530 | [diff] [blame] | 74 | enum me_fw_sku { |
| 75 | ME_HFS3_FW_SKU_CONSUMER = 0x2, |
| 76 | ME_HFS3_FW_SKU_CORPORATE = 0x3, |
| 77 | ME_HFS3_FW_SKU_LITE = 0x5, |
| 78 | }; |
Sridhar Siricilla | 3d27705 | 2020-02-06 14:21:49 +0530 | [diff] [blame] | 79 | |
Bora Guvendik | f33c9bf | 2021-11-05 23:09:25 -0700 | [diff] [blame] | 80 | /* Number of cse boot performance data */ |
| 81 | #define NUM_CSE_BOOT_PERF_DATA 64 |
| 82 | |
Anil Kumar | 7b2edc3 | 2023-04-18 11:03:34 -0700 | [diff] [blame] | 83 | /* PSR_HECI_FW_DOWNGRADE_BACKUP Command */ |
| 84 | #define PSR_HECI_FW_DOWNGRADE_BACKUP 0x3 |
| 85 | |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 86 | /* HFSTS register offsets in PCI config space */ |
| 87 | enum { |
| 88 | PCI_ME_HFSTS1 = 0x40, |
| 89 | PCI_ME_HFSTS2 = 0x48, |
| 90 | PCI_ME_HFSTS3 = 0x60, |
| 91 | PCI_ME_HFSTS4 = 0x64, |
| 92 | PCI_ME_HFSTS5 = 0x68, |
| 93 | PCI_ME_HFSTS6 = 0x6C, |
| 94 | }; |
| 95 | |
Dinesh Gehlot | f963feb | 2023-03-24 06:39:33 +0000 | [diff] [blame] | 96 | /* CSE partition list */ |
| 97 | enum fpt_partition_id { |
| 98 | FPT_PARTITION_NAME_UNDEFINED = 0x0, |
| 99 | FPT_PARTITION_NAME_ISHC = 0x43485349, |
| 100 | }; |
| 101 | |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 102 | /* MKHI Message Header */ |
Sridhar Siricilla | f35eee9 | 2019-09-23 19:38:21 +0530 | [diff] [blame] | 103 | struct mkhi_hdr { |
| 104 | uint8_t group_id; |
| 105 | uint8_t command:7; |
| 106 | uint8_t is_resp:1; |
| 107 | uint8_t rsvd; |
| 108 | uint8_t result; |
| 109 | } __packed; |
| 110 | |
Anil Kumar | 7b2edc3 | 2023-04-18 11:03:34 -0700 | [diff] [blame] | 111 | /* PSR HECI message status */ |
| 112 | enum psr_status { |
| 113 | PSR_STATUS_SUCCESS, |
| 114 | PSR_STATUS_FEATURE_NOT_SUPPORTED, |
| 115 | PSR_STATUS_UPID_DISABLED, |
| 116 | PSR_STATUS_ACTION_NOT_ALLOWED, |
| 117 | PSR_STATUS_INVALID_INPUT_PARAMETER, |
| 118 | PSR_STATUS_INTERNAL_ERROR, |
| 119 | PSR_STATUS_NOT_ALLOWED_AFTER_EOP, |
| 120 | }; |
| 121 | |
| 122 | /* PSR HECI message header */ |
| 123 | struct psr_heci_header { |
| 124 | uint8_t command; |
| 125 | uint8_t reserved; |
| 126 | uint16_t length; |
| 127 | } __packed; |
| 128 | |
V Sowmya | 338b83c | 2020-11-11 07:04:13 +0530 | [diff] [blame] | 129 | /* CSE FW Version */ |
| 130 | struct fw_version { |
| 131 | uint16_t major; |
| 132 | uint16_t minor; |
| 133 | uint16_t hotfix; |
| 134 | uint16_t build; |
| 135 | } __packed; |
| 136 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 137 | /* ME FW Version */ |
| 138 | struct me_version { |
| 139 | uint16_t minor; |
| 140 | uint16_t major; |
| 141 | uint16_t build; |
| 142 | uint16_t hotfix; |
| 143 | } __packed; |
| 144 | |
| 145 | /* ME FW Version response */ |
| 146 | struct me_fw_ver_resp { |
| 147 | struct mkhi_hdr hdr; |
| 148 | struct me_version code; |
| 149 | struct me_version rec; |
| 150 | struct me_version fitc; |
| 151 | } __packed; |
| 152 | |
Dinesh Gehlot | f963feb | 2023-03-24 06:39:33 +0000 | [diff] [blame] | 153 | /* Module data from manifest */ |
| 154 | struct flash_partition_data { |
| 155 | enum fpt_partition_id partition_id; |
| 156 | uint8_t reserved1[8]; |
| 157 | struct fw_version version; |
| 158 | uint32_t vendor_id; |
| 159 | uint32_t tcb_svn; |
| 160 | uint32_t arb_svn; |
| 161 | uint32_t vcn; |
| 162 | uint32_t reserved2[13]; |
| 163 | }; |
| 164 | |
| 165 | /* Response header for partition information request */ |
| 166 | struct fw_version_resp { |
| 167 | struct mkhi_hdr hdr; |
| 168 | uint32_t module_count; |
| 169 | struct flash_partition_data manifest_data; |
| 170 | }; |
| 171 | |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 172 | /* ISHC version */ |
| 173 | struct cse_fw_ish_version_info { |
| 174 | struct fw_version prev_cse_fw_version; |
| 175 | struct fw_version cur_ish_fw_version; |
| 176 | }; |
| 177 | |
| 178 | /* CSE and ISHC version */ |
| 179 | struct cse_fw_partition_info { |
| 180 | struct fw_version cur_cse_fw_version; |
| 181 | struct cse_fw_ish_version_info ish_partition_info; |
| 182 | }; |
| 183 | |
Subrata Banik | 65a6d17 | 2023-08-13 13:03:50 +0000 | [diff] [blame] | 184 | /* CSE Specific Information */ |
| 185 | struct cse_specific_info { |
| 186 | struct cse_fw_partition_info cse_fwp_version; |
| 187 | bool cse_downgrade_requested; |
| 188 | uint32_t crc; |
| 189 | }; |
| 190 | |
Krishna Prasad Bhat | 98fb5ff | 2023-07-18 21:49:17 +0530 | [diff] [blame] | 191 | /* PSR backup status */ |
| 192 | enum psr_backup_state { |
| 193 | PSR_BACKUP_DONE = 0, |
| 194 | PSR_BACKUP_PENDING = 1, |
| 195 | }; |
| 196 | |
| 197 | struct psr_backup_status { |
| 198 | uint32_t signature; |
| 199 | int8_t value; |
| 200 | uint16_t checksum; |
| 201 | }; |
| 202 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 203 | /* CSE RX and TX error status */ |
| 204 | enum cse_tx_rx_status { |
| 205 | /* |
| 206 | * Transmission of HECI message is success or |
| 207 | * Reception of HECI message is success. |
| 208 | */ |
| 209 | CSE_TX_RX_SUCCESS = 0, |
| 210 | |
| 211 | /* Timeout to send a message to CSE */ |
| 212 | CSE_TX_ERR_TIMEOUT = 1, |
| 213 | |
| 214 | /* Timeout to receive the response message from CSE */ |
| 215 | CSE_RX_ERR_TIMEOUT = 2, |
| 216 | |
| 217 | /* |
| 218 | * Response length doesn't match with expected |
| 219 | * response message length |
| 220 | */ |
| 221 | CSE_RX_ERR_RESP_LEN_MISMATCH = 3, |
| 222 | |
| 223 | /* CSE is not ready during TX flow */ |
| 224 | CSE_TX_ERR_CSE_NOT_READY = 4, |
| 225 | |
| 226 | /* CSE is not ready during RX flow */ |
| 227 | CSE_RX_ERR_CSE_NOT_READY = 5, |
| 228 | |
| 229 | /* Invalid input arguments provided for TX API */ |
| 230 | CSE_TX_ERR_INPUT = 6, |
| 231 | |
| 232 | /* Invalid input arguments provided for RX API */ |
| 233 | CSE_RX_ERR_INPUT = 7, |
| 234 | }; |
| 235 | |
Tim Wawrzynczak | e380a43 | 2021-06-18 09:54:55 -0600 | [diff] [blame] | 236 | /* CSE recovery sub-error codes */ |
| 237 | enum csme_failure_reason { |
| 238 | /* No error */ |
| 239 | CSE_NO_ERROR = 0, |
| 240 | |
| 241 | /* Unspecified error */ |
| 242 | CSE_ERROR_UNSPECIFIED = 1, |
| 243 | |
| 244 | /* CSE fails to boot from RW */ |
| 245 | CSE_LITE_SKU_RW_JUMP_ERROR = 2, |
| 246 | |
| 247 | /* CSE RW boot partition access error */ |
| 248 | CSE_LITE_SKU_RW_ACCESS_ERROR = 3, |
| 249 | |
| 250 | /* Fails to set next boot partition as RW */ |
| 251 | CSE_LITE_SKU_RW_SWITCH_ERROR = 4, |
| 252 | |
| 253 | /* CSE firmware update failure */ |
| 254 | CSE_LITE_SKU_FW_UPDATE_ERROR = 5, |
| 255 | |
| 256 | /* Fails to communicate with CSE */ |
| 257 | CSE_COMMUNICATION_ERROR = 6, |
| 258 | |
| 259 | /* Fails to wipe CSE runtime data */ |
| 260 | CSE_LITE_SKU_DATA_WIPE_ERROR = 7, |
| 261 | |
| 262 | /* CSE RW is not found */ |
| 263 | CSE_LITE_SKU_RW_BLOB_NOT_FOUND = 8, |
| 264 | |
| 265 | /* CSE CBFS RW SHA-256 mismatch with the provided SHA */ |
| 266 | CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH = 9, |
| 267 | |
| 268 | /* CSE CBFS RW metadata is not found */ |
| 269 | CSE_LITE_SKU_RW_METADATA_NOT_FOUND = 10, |
| 270 | |
| 271 | /* CSE CBFS RW blob layout is not correct */ |
| 272 | CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR = 11, |
Tim Wawrzynczak | 064ca18 | 2021-06-17 12:40:13 -0600 | [diff] [blame] | 273 | |
| 274 | /* Error sending EOP to CSE */ |
| 275 | CSE_EOP_FAIL = 12, |
Krishna Prasad Bhat | 333edcc | 2021-11-26 06:52:27 +0530 | [diff] [blame] | 276 | |
| 277 | /* CSE Sub-partition update fail */ |
| 278 | CSE_LITE_SKU_SUB_PART_UPDATE_FAIL = 13, |
| 279 | |
| 280 | /* CSE sub-partition access failure */ |
| 281 | CSE_LITE_SKU_SUB_PART_ACCESS_ERR = 14, |
| 282 | |
| 283 | /* CSE CBFS sub-partition access error */ |
| 284 | CSE_LITE_SKU_SUB_PART_BLOB_ACCESS_ERR = 15, |
| 285 | |
| 286 | /* CSE Lite sub-partition update is not required */ |
| 287 | CSE_LITE_SKU_SUB_PART_UPDATE_NOT_REQ = 16, |
| 288 | |
| 289 | /* CSE Lite sub-partition layout mismatch error */ |
| 290 | CSE_LITE_SKU_SUB_PART_LAYOUT_MISMATCH_ERROR = 17, |
| 291 | |
| 292 | /* CSE Lite sub-partition update success */ |
| 293 | CSE_LITE_SKU_PART_UPDATE_SUCCESS = 18, |
Tim Wawrzynczak | e380a43 | 2021-06-18 09:54:55 -0600 | [diff] [blame] | 294 | }; |
| 295 | |
Bora Guvendik | f33c9bf | 2021-11-05 23:09:25 -0700 | [diff] [blame] | 296 | /* CSE boot performance data */ |
| 297 | struct cse_boot_perf_rsp { |
| 298 | struct mkhi_hdr hdr; |
| 299 | |
| 300 | /* Data version */ |
| 301 | uint32_t version; |
| 302 | |
| 303 | /* Data length in DWORDs, represents number of valid elements in timestamp array */ |
| 304 | uint32_t num_valid_timestamps; |
| 305 | |
| 306 | /* Boot performance data */ |
| 307 | uint32_t timestamp[NUM_CSE_BOOT_PERF_DATA]; |
| 308 | } __packed; |
| 309 | |
Subrata Banik | 0b92aa6 | 2022-06-01 06:54:44 +0000 | [diff] [blame] | 310 | /* |
| 311 | * Initialize the CSE device. |
| 312 | * |
| 313 | * Set up CSE device for use in early boot environment with temp bar. |
| 314 | */ |
| 315 | void cse_init(uintptr_t bar); |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 316 | |
Subrata Banik | 801dbf4 | 2022-06-01 07:56:40 +0000 | [diff] [blame] | 317 | /* Initialize the HECI devices. */ |
| 318 | void heci_init(void); |
| 319 | |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 320 | /* |
Jeremy Compostella | 0e1be04 | 2023-03-13 13:41:43 -0700 | [diff] [blame] | 321 | * Send message msg of size len to host from host_addr to cse_addr. |
| 322 | * Returns CSE_TX_RX_SUCCESS on success and other enum values on failure scenarios. |
| 323 | * Also, in case of errors, heci_reset() is triggered. |
| 324 | */ |
| 325 | enum cse_tx_rx_status heci_send(const void *msg, size_t len, uint8_t host_addr, |
| 326 | uint8_t client_addr); |
| 327 | |
| 328 | /* |
| 329 | * Receive message into buff not exceeding maxlen. Message is considered |
| 330 | * successfully received if a 'complete' indication is read from ME side |
| 331 | * and there was enough space in the buffer to fit that message. maxlen |
| 332 | * is updated with size of message that was received. |
| 333 | * Returns CSE_TX_RX_SUCCESS on success and other enum values on failure scenarios. |
| 334 | * Also, in case of errors, heci_reset() is triggered. |
| 335 | */ |
| 336 | enum cse_tx_rx_status heci_receive(void *buff, size_t *maxlen); |
| 337 | |
| 338 | /* |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 339 | * Send message from BIOS_HOST_ADDR to cse_addr. |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 340 | * Sends snd_msg of size snd_sz, and reads message into buffer pointed by |
| 341 | * rcv_msg of size rcv_sz |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 342 | * Returns CSE_TX_RX_SUCCESS on success and other enum values on failure scenarios. |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 343 | */ |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 344 | enum cse_tx_rx_status heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, |
| 345 | size_t *rcv_sz, uint8_t cse_addr); |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 346 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 347 | /* |
| 348 | * Attempt device reset. This is useful and perhaps only thing left to do when |
| 349 | * CPU and CSE are out of sync or CSE fails to respond. |
Sridhar Siricilla | 1d20cfa | 2020-01-12 12:29:15 +0530 | [diff] [blame] | 350 | * Returns 0 on failure and 1 on success. |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 351 | */ |
| 352 | int heci_reset(void); |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 353 | /* Disable HECI1 using Sideband interface communication */ |
| 354 | void heci1_disable(void); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 355 | |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 356 | /* Reads config value from a specified offset in the CSE PCI Config space. */ |
| 357 | uint32_t me_read_config32(int offset); |
| 358 | |
| 359 | /* |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 360 | * Check if the CSE device as per function argument `devfn` is enabled in device tree |
| 361 | * and also visible on the PCI bus. |
| 362 | */ |
| 363 | bool is_cse_devfn_visible(unsigned int devfn); |
| 364 | |
| 365 | /* |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 366 | * Check if the CSE device is enabled in device tree. Also check if the device |
| 367 | * is visible on the PCI bus by reading config space. |
| 368 | * Return true if device present and config space enabled, else return false. |
| 369 | */ |
| 370 | bool is_cse_enabled(void); |
| 371 | |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 372 | /* Makes the host ready to communicate with CSE */ |
| 373 | void cse_set_host_ready(void); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 374 | |
| 375 | /* |
| 376 | * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds. |
Sridhar Siricilla | 1d20cfa | 2020-01-12 12:29:15 +0530 | [diff] [blame] | 377 | * Returns 0 on failure and 1 on success. |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 378 | */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 379 | uint8_t cse_wait_sec_override_mode(void); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 380 | |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 381 | enum rst_req_type { |
| 382 | GLOBAL_RESET = 1, |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 383 | CSE_RESET_ONLY = 3, |
| 384 | }; |
| 385 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 386 | /* |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 387 | * Sends GLOBAL_RESET_REQ cmd to CSE with reset type GLOBAL_RESET. |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 388 | * Returns 0 on failure and 1 on success. |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 389 | */ |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 390 | int cse_request_global_reset(void); |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 391 | /* |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 392 | * Sends HMRFPO_ENABLE command. |
| 393 | * HMRFPO - Host ME Region Flash Protection Override. |
Sridhar Siricilla | 6ad7010 | 2020-05-12 21:28:53 +0530 | [diff] [blame] | 394 | * For CSE Lite SKU, procedure to place CSE in HMRFPO (SECOVER_MEI_MSG) mode: |
| 395 | * 1. Ensure CSE boots from RO(BP1). |
| 396 | * - Set CSE's next boot partition to RO |
| 397 | * - Issue GLOBAL_RESET command to reset the system |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 398 | * 2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required. |
| 399 | * |
| 400 | * The HMRFPO mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks |
| 401 | * the CSE region to perform updates to it. |
| 402 | * This command is only valid before EOP. |
| 403 | * |
| 404 | * Returns 0 on failure to send HECI command and to enable HMRFPO mode, and 1 on success. |
| 405 | * |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 406 | */ |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 407 | enum cb_err cse_hmrfpo_enable(void); |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 408 | |
| 409 | /* |
| 410 | * Send HMRFPO_GET_STATUS command. |
| 411 | * returns -1 on failure and 0 (DISABLED)/ 1 (LOCKED)/ 2 (ENABLED) |
| 412 | * on success. |
| 413 | */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 414 | int cse_hmrfpo_get_status(void); |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 415 | |
Sridhar Siricilla | 83af733 | 2020-01-08 00:13:21 +0530 | [diff] [blame] | 416 | /* Fixed Address MEI Header's Host Address field value */ |
| 417 | #define BIOS_HOST_ADDR 0x00 |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 418 | |
Sridhar Siricilla | 83af733 | 2020-01-08 00:13:21 +0530 | [diff] [blame] | 419 | /* Fixed Address MEI Header's ME Address field value */ |
| 420 | #define HECI_MKHI_ADDR 0x07 |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 421 | |
Anil Kumar | 7b2edc3 | 2023-04-18 11:03:34 -0700 | [diff] [blame] | 422 | /* Fixed Address MEI Header's ME Address field value for PSR messages */ |
| 423 | #define HECI_PSR_ADDR 0x04 |
| 424 | |
Tim Wawrzynczak | 9fdd2b2 | 2021-06-18 10:34:09 -0600 | [diff] [blame] | 425 | /* Fixed Address MEI Header's ME Address for MEI bus messages */ |
| 426 | #define HECI_MEI_ADDR 0x00 |
| 427 | |
Sridhar Siricilla | 83af733 | 2020-01-08 00:13:21 +0530 | [diff] [blame] | 428 | /* HMRFPO Status types */ |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 429 | /* Host can't access ME region */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 430 | #define MKHI_HMRFPO_DISABLED 0 |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 431 | |
| 432 | /* |
| 433 | * ME Firmware locked down HMRFPO Feature. |
| 434 | * Host can't access ME region. |
| 435 | */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 436 | #define MKHI_HMRFPO_LOCKED 1 |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 437 | |
| 438 | /* Host can access ME region */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 439 | #define MKHI_HMRFPO_ENABLED 2 |
| 440 | |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 441 | /* |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 442 | * Queries and logs ME firmware version |
| 443 | */ |
| 444 | void print_me_fw_version(void *unused); |
| 445 | |
| 446 | /* |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 447 | * Queries and gets ME firmware version |
| 448 | */ |
| 449 | enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp); |
| 450 | |
| 451 | /* |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 452 | * Checks current working operation state is normal or not. |
| 453 | * Returns true if CSE's current working state is normal, otherwise false. |
| 454 | */ |
| 455 | bool cse_is_hfs1_cws_normal(void); |
| 456 | |
| 457 | /* |
| 458 | * Checks CSE's current operation mode is normal or not. |
| 459 | * Returns true if CSE's current operation mode is normal, otherwise false. |
| 460 | */ |
| 461 | bool cse_is_hfs1_com_normal(void); |
| 462 | |
| 463 | /* |
| 464 | * Checks CSE's current operation mode is SECOVER_MEI_MSG or not. |
| 465 | * Returns true if CSE's current operation mode is SECOVER_MEI_MSG, otherwise false. |
| 466 | */ |
| 467 | bool cse_is_hfs1_com_secover_mei_msg(void); |
| 468 | |
| 469 | /* |
| 470 | * Checks CSE's current operation mode is Soft Disable Mode or not. |
| 471 | * Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false. |
| 472 | */ |
| 473 | bool cse_is_hfs1_com_soft_temp_disable(void); |
| 474 | |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 475 | /* |
Subrata Banik | e74ebcd | 2021-12-27 10:49:19 +0000 | [diff] [blame] | 476 | * Checks CSE's spi protection mode is protected or unprotected. |
| 477 | * Returns true if CSE's spi protection mode is protected, otherwise false. |
| 478 | */ |
| 479 | bool cse_is_hfs1_spi_protected(void); |
| 480 | |
| 481 | /* |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 482 | * Checks CSE's Firmware SKU is Lite or not. |
| 483 | * Returns true if CSE's Firmware SKU is Lite, otherwise false |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 484 | */ |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 485 | bool cse_is_hfs3_fw_sku_lite(void); |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 486 | |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 487 | /* |
| 488 | * Polls for CSE's current operation mode 'Soft Temp Disable'. |
| 489 | * Returns 0 on failure and 1 on success. |
| 490 | */ |
| 491 | uint8_t cse_wait_com_soft_temp_disable(void); |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 492 | |
| 493 | /* |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 494 | * The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set |
Jon Murphy | c4e9045 | 2022-06-28 10:36:23 -0600 | [diff] [blame] | 495 | * CSE's boot partition as per ChromeOS boot modes. In normal mode, the function allows CSE to |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 496 | * boot from RW and triggers recovery mode if CSE fails to jump to RW. |
| 497 | * In software triggered recovery mode, the function allows CSE to boot from whatever is |
| 498 | * currently selected partition. |
| 499 | */ |
Sridhar Siricilla | 1a2b702 | 2020-12-04 02:22:28 +0530 | [diff] [blame] | 500 | void cse_fw_sync(void); |
Karthikeyan Ramasubramanian | f9cc637 | 2020-08-04 16:38:58 -0600 | [diff] [blame] | 501 | |
| 502 | /* Perform a board-specific reset sequence for CSE RO<->RW jump */ |
| 503 | void cse_board_reset(void); |
| 504 | |
Jeremy Compostella | 08b5200d | 2023-01-19 11:32:25 -0700 | [diff] [blame] | 505 | /* Perform a misc operation before CSE firmware update. */ |
| 506 | void cse_fw_update_misc_oper(void); |
| 507 | |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 508 | /* Trigger vboot recovery mode on a CSE error */ |
| 509 | void cse_trigger_vboot_recovery(enum csme_failure_reason reason); |
| 510 | |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 511 | enum cse_device_state { |
| 512 | DEV_IDLE, |
| 513 | DEV_ACTIVE, |
| 514 | }; |
| 515 | |
| 516 | /* Function to get the current CSE device state as per `cse_device_state` */ |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 517 | enum cse_device_state get_cse_device_state(unsigned int devfn); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 518 | |
| 519 | /* Function that put the CSE into desired state based on `requested_state` */ |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 520 | bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 521 | |
Krishna Prasad Bhat | 333edcc | 2021-11-26 06:52:27 +0530 | [diff] [blame] | 522 | /* |
| 523 | * Check if cse sub-parition update is required or not. |
| 524 | * Returns true if cse sub-parition update is required otherwise false. |
| 525 | */ |
| 526 | bool skip_cse_sub_part_update(void); |
Bora Guvendik | f33c9bf | 2021-11-05 23:09:25 -0700 | [diff] [blame] | 527 | |
| 528 | /* |
| 529 | * This command retrieves a set of boot performance timestamps CSME collected during |
| 530 | * the last platform boot flow. |
| 531 | */ |
Sridhar Siricilla | dd7d51d | 2023-01-10 15:05:07 +0530 | [diff] [blame] | 532 | enum cb_err cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf); |
Bora Guvendik | f33c9bf | 2021-11-05 23:09:25 -0700 | [diff] [blame] | 533 | |
Subrata Banik | 736f9cc | 2022-01-27 20:52:46 +0530 | [diff] [blame] | 534 | /* Function to make cse disable using PMC IPC */ |
| 535 | bool cse_disable_mei_devices(void); |
| 536 | |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 537 | /* Set CSE device state to D0I3 */ |
| 538 | void cse_set_to_d0i3(void); |
| 539 | |
| 540 | /* Function sets D0I3 for all HECI devices */ |
| 541 | void heci_set_to_d0i3(void); |
| 542 | |
Subrata Banik | 80c9289 | 2022-02-01 00:26:55 +0530 | [diff] [blame] | 543 | /* Function performs the global reset lock */ |
| 544 | void cse_control_global_reset_lock(void); |
| 545 | |
Subrata Banik | 7c31d17 | 2022-02-01 00:11:29 +0530 | [diff] [blame] | 546 | /* Send End of Post (EOP) command to CSE device */ |
| 547 | void cse_send_end_of_post(void); |
| 548 | |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 549 | /* |
Subrata Banik | 17a3da8 | 2022-11-24 21:51:42 +0530 | [diff] [blame] | 550 | * This function to perform essential post EOP cse related operations |
| 551 | * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config |
| 552 | */ |
| 553 | void cse_late_finalize(void); |
| 554 | |
| 555 | /* |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 556 | * SoC override API to make heci1 disable using PCR. |
| 557 | * |
| 558 | * Allow SoC to implement heci1 disable override due to PSF registers being |
| 559 | * different across SoC generation. |
| 560 | */ |
| 561 | void soc_disable_heci1_using_pcr(void); |
| 562 | |
Bora Guvendik | 860672e | 2021-09-26 17:25:48 -0700 | [diff] [blame] | 563 | /* |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 564 | * SoC override API to identify if ISH Firmware existed inside CSE FPT. |
| 565 | * |
| 566 | * This override is required to avoid making default call into non-ISH |
| 567 | * supported SKU to attempt to retrieve ISH version which would results into |
| 568 | * increased boot time by 100ms+. |
| 569 | * |
| 570 | * Ideally SoC with UFS enabled would like to keep ISH enabled as well, hence |
| 571 | * identifying the UFS enabled device is enough to conclude if ISH partition is |
| 572 | * available. |
| 573 | */ |
Subrata Banik | 272ce9a | 2023-06-13 00:44:44 +0530 | [diff] [blame] | 574 | #if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION) |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 575 | bool soc_is_ish_partition_enabled(void); |
| 576 | #else |
| 577 | static inline bool soc_is_ish_partition_enabled(void) |
| 578 | { |
| 579 | /* Default implementation, ISH not enabled. */ |
| 580 | return false; |
| 581 | } |
| 582 | #endif |
| 583 | |
| 584 | /* |
Bora Guvendik | 9405049 | 2023-03-12 12:24:58 -0700 | [diff] [blame] | 585 | * Injects CSE timestamps into cbmem timestamp table. SoC code needs to |
| 586 | * implement it since timestamp definitions differ from SoC to SoC. |
| 587 | */ |
| 588 | void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time); |
| 589 | |
| 590 | /* |
Bora Guvendik | 860672e | 2021-09-26 17:25:48 -0700 | [diff] [blame] | 591 | * Get all the timestamps CSE collected using cse_get_boot_performance_data() and |
| 592 | * insert them into the CBMEM timestamp table. |
| 593 | */ |
| 594 | void cse_get_telemetry_data(void); |
| 595 | |
Subrata Banik | da527ec | 2022-11-24 15:42:35 +0530 | [diff] [blame] | 596 | /* Function to log the cse WP information like range, if WP etc. */ |
| 597 | void cse_log_ro_write_protection_info(bool mfg_mode); |
| 598 | |
Michał Żygowski | daa1710 | 2022-10-04 10:55:38 +0200 | [diff] [blame] | 599 | /* |
| 600 | * Changes Intel PTT feature state at runtime. Global reset is required after |
| 601 | * successful HECI command completion. |
| 602 | */ |
| 603 | void cse_enable_ptt(bool state); |
| 604 | |
| 605 | /* |
| 606 | * Queries CSE for runtime status of firmware features. |
| 607 | * Returns 0 on success and < 0 on failure. |
| 608 | */ |
| 609 | enum cb_err cse_get_fw_feature_state(uint32_t *feature_state); |
| 610 | |
Krishna Prasad Bhat | 4f062ec | 2023-09-21 23:33:34 +0530 | [diff] [blame] | 611 | /* Fills the CSE Boot Partition Info response */ |
| 612 | void cse_fill_bp_info(void); |
| 613 | |
Sridhar Siricilla | 83af733 | 2020-01-08 00:13:21 +0530 | [diff] [blame] | 614 | #endif // SOC_INTEL_COMMON_CSE_H |