Angel Pons | cc98db3 | 2020-04-05 13:22:27 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 2 | |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 3 | #include <arch/exception.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 4 | #include <armv7.h> |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 5 | #include <boot_device.h> |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 6 | #include <cbmem.h> |
Aaron Durbin | dc9f5cd | 2015-09-08 13:34:43 -0500 | [diff] [blame] | 7 | #include <commonlib/region.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 8 | #include <console/console.h> |
Nico Huber | 0f2dd1e | 2017-08-01 14:02:40 +0200 | [diff] [blame] | 9 | #include <device/i2c_simple.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 10 | #include <drivers/maxim/max77802/max77802.h> |
| 11 | #include <program_loading.h> |
Arthur Heymans | 3e914d3 | 2022-04-06 22:25:50 +0200 | [diff] [blame] | 12 | #include <romstage_common.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 13 | #include <soc/clk.h> |
| 14 | #include <soc/cpu.h> |
| 15 | #include <soc/dmc.h> |
| 16 | #include <soc/gpio.h> |
| 17 | #include <soc/i2c.h> |
| 18 | #include <soc/periph.h> |
| 19 | #include <soc/power.h> |
| 20 | #include <soc/setup.h> |
| 21 | #include <soc/trustzone.h> |
| 22 | #include <soc/wakeup.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 23 | #include <timestamp.h> |
| 24 | #include <types.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 25 | |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 26 | #define PMIC_I2C_BUS 4 |
| 27 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 28 | struct pmic_write |
| 29 | { |
| 30 | int or_orig; // Whether to or in the original value. |
| 31 | uint8_t reg; // Register to write. |
| 32 | uint8_t val; // Value to write. |
| 33 | }; |
| 34 | |
| 35 | /* |
| 36 | * Use read-modify-write for MAX77802 control registers and clobber the |
| 37 | * output voltage setting (BUCK?DVS?) registers. |
| 38 | */ |
| 39 | struct pmic_write pmic_writes[] = |
| 40 | { |
| 41 | { 1, MAX77802_REG_PMIC_32KHZ, MAX77802_32KHCP_EN }, |
| 42 | { 0, MAX77802_REG_PMIC_BUCK1DVS1, MAX77802_BUCK1DVS1_1V }, |
| 43 | { 1, MAX77802_REG_PMIC_BUCK1CTRL, MAX77802_BUCK_TYPE1_ON | |
| 44 | MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, |
David Hendricks | 1f9f04e | 2013-08-01 18:57:52 -0700 | [diff] [blame] | 45 | { 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1_2625V }, |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 46 | { 1, MAX77802_REG_PMIC_BUCK2CTRL1, MAX77802_BUCK_TYPE2_ON | |
| 47 | MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, |
| 48 | { 0, MAX77802_REG_PMIC_BUCK3DVS1, MAX77802_BUCK3DVS1_1V }, |
| 49 | { 1, MAX77802_REG_PMIC_BUCK3CTRL1, MAX77802_BUCK_TYPE2_ON | |
| 50 | MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, |
| 51 | { 0, MAX77802_REG_PMIC_BUCK4DVS1, MAX77802_BUCK4DVS1_1V }, |
| 52 | { 1, MAX77802_REG_PMIC_BUCK4CTRL1, MAX77802_BUCK_TYPE2_ON | |
| 53 | MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, |
| 54 | { 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V }, |
| 55 | { 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON | |
Ronald G. Minnich | 88ac9b5 | 2013-06-26 17:28:52 -0700 | [diff] [blame] | 56 | MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, |
David Hendricks | 1f9f04e | 2013-08-01 18:57:52 -0700 | [diff] [blame] | 57 | /* Disable Boost(bypass) OUTPUT */ |
| 58 | { 0, MAX77802_REG_PMIC_BOOSTCTRL, MAX77802_BOOSTCTRL_OFF}, |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 59 | }; |
| 60 | |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 61 | static int setup_power(int is_resume) |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 62 | { |
| 63 | int error = 0; |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 64 | int i; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 65 | |
| 66 | power_init(); |
| 67 | |
Hung-Te Lin | da7b8e4 | 2013-06-28 17:27:17 +0800 | [diff] [blame] | 68 | if (is_resume) { |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 69 | return 0; |
Hung-Te Lin | da7b8e4 | 2013-06-28 17:27:17 +0800 | [diff] [blame] | 70 | } |
| 71 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 72 | /* Initialize I2C bus to configure PMIC. */ |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 73 | exynos_pinmux_i2c4(); |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 74 | i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 75 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 76 | for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { |
| 77 | uint8_t data = 0; |
| 78 | uint8_t reg = pmic_writes[i].reg; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 79 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 80 | if (pmic_writes[i].or_orig) |
Gabe Black | cdb61a6 | 2014-04-07 18:45:14 -0700 | [diff] [blame] | 81 | error |= i2c_readb(4, MAX77802_I2C_ADDR, reg, &data); |
| 82 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 83 | data |= pmic_writes[i].val; |
Gabe Black | cdb61a6 | 2014-04-07 18:45:14 -0700 | [diff] [blame] | 84 | error |= i2c_writeb(4, MAX77802_I2C_ADDR, reg, data); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 85 | } |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 86 | |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 87 | return error; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 88 | } |
| 89 | |
Hung-Te Lin | c357aed | 2013-06-24 20:02:01 +0800 | [diff] [blame] | 90 | static void setup_ec(void) |
| 91 | { |
| 92 | /* SPI2 (EC) is slower and needs to work in half-duplex mode with |
| 93 | * single byte bus width. */ |
Gabe Black | 9801809 | 2013-07-24 06:18:20 -0700 | [diff] [blame] | 94 | clock_set_rate(PERIPH_ID_SPI2, 5000000); |
Hung-Te Lin | c357aed | 2013-06-24 20:02:01 +0800 | [diff] [blame] | 95 | exynos_pinmux_spi2(); |
| 96 | } |
| 97 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 98 | static void setup_gpio(void) |
| 99 | { |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 100 | gpio_direction_input(GPIO_X30); // WP_GPIO |
| 101 | gpio_set_pull(GPIO_X30, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 102 | |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 103 | gpio_direction_input(GPIO_X07); // RECMODE_GPIO |
| 104 | gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 105 | |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 106 | gpio_direction_input(GPIO_X34); // LID_GPIO |
| 107 | gpio_set_pull(GPIO_X34, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 108 | |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 109 | gpio_direction_input(GPIO_X12); // POWER_GPIO |
| 110 | gpio_set_pull(GPIO_X12, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | static void setup_memory(struct mem_timings *mem, int is_resume) |
| 114 | { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 115 | printk(BIOS_SPEW, "manufacturer: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 116 | mem->mem_manuf, |
| 117 | mem->mem_type, |
| 118 | mem->mpll_mdiv, |
| 119 | mem->frequency_mhz); |
| 120 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 121 | if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { |
| 122 | die("Failed to initialize memory controller.\n"); |
| 123 | } |
| 124 | } |
| 125 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 126 | #define PRIMITIVE_MEM_TEST 0 |
| 127 | #if PRIMITIVE_MEM_TEST |
| 128 | static unsigned long primitive_mem_test(void) |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 129 | { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 130 | unsigned long *l = (void *)0x40000000; |
| 131 | int bad = 0; |
| 132 | unsigned long i; |
Elyes HAOUAS | 5ba154a | 2020-08-04 13:27:52 +0200 | [diff] [blame] | 133 | for (i = 0; i < 256*1048576; i++){ |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 134 | if (! (i%1048576)) |
| 135 | printk(BIOS_SPEW, "%lu ...", i); |
| 136 | l[i] = 0xffffffff - i; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 137 | } |
Gabe Black | 5420e09 | 2013-05-17 11:29:22 -0700 | [diff] [blame] | 138 | |
Elyes HAOUAS | 5ba154a | 2020-08-04 13:27:52 +0200 | [diff] [blame] | 139 | for (i = 0; i < 256*1048576; i++){ |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 140 | if (! (i%1048576)) |
| 141 | printk(BIOS_SPEW, "%lu ...", i); |
| 142 | if (l[i] != (0xffffffff - i)){ |
| 143 | printk(BIOS_SPEW, "%p: want %08lx got %08lx\n", l, l[i], 0xffffffff - i); |
| 144 | bad++; |
| 145 | } |
| 146 | } |
Gabe Black | 5420e09 | 2013-05-17 11:29:22 -0700 | [diff] [blame] | 147 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 148 | printk(BIOS_SPEW, "%d errors\n", bad); |
| 149 | |
| 150 | return bad; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 151 | } |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 152 | #else |
| 153 | #define primitive_mem_test() |
| 154 | #endif |
| 155 | |
| 156 | #define SIMPLE_SPI_TEST 0 |
| 157 | #if SIMPLE_SPI_TEST |
| 158 | /* here is a simple SPI debug test, known to fid trouble */ |
| 159 | static void simple_spi_test(void) |
| 160 | { |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 161 | const struct region_device *boot_dev; |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 162 | int i, amt = 4 * MiB, errors = 0; |
| 163 | //u32 *data = (void *)0x40000000; |
| 164 | u32 data[1024]; |
| 165 | u32 in; |
| 166 | |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 167 | boot_device_init(); |
| 168 | boot_dev = boot_device_ro(); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 169 | amt = sizeof(data); |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 170 | if (boot_dev == NULL) { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 171 | printk(BIOS_SPEW, "Failed to initialize default media.\n"); |
| 172 | return; |
| 173 | } |
| 174 | |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 175 | if (rdev_readat(boot_dev, data, 0, amt) < amt) { |
Elyes Haouas | 39efcd1 | 2023-01-22 11:53:56 +0100 | [diff] [blame] | 176 | printk(BIOS_SPEW, "%s fails\n", __func__); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 177 | return; |
| 178 | } |
| 179 | |
Elyes HAOUAS | 5ba154a | 2020-08-04 13:27:52 +0200 | [diff] [blame] | 180 | for (i = 0; i < amt; i += 4){ |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 181 | if (rdev_readat(boot_dev, &in, i, 4) < 4) { |
Elyes Haouas | 39efcd1 | 2023-01-22 11:53:56 +0100 | [diff] [blame] | 182 | printk(BIOS_SPEW, "%s fails at %d\n", __func__, i); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 183 | return; |
| 184 | } |
| 185 | if (data[i/4] != in){ |
| 186 | errors++; |
| 187 | printk(BIOS_SPEW, "BAD at %d(%p):\nRAM %08lx\nSPI %08lx\n", |
| 188 | i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); |
| 189 | /* reread it to see which is wrong. */ |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 190 | if (rdev_readat(boot_dev, &in, i, 4) < 4) { |
Elyes Haouas | 39efcd1 | 2023-01-22 11:53:56 +0100 | [diff] [blame] | 191 | printk(BIOS_SPEW, "%s fails at %d\n", __func__, i); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 192 | return; |
| 193 | } |
| 194 | printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n", |
| 195 | i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); |
| 196 | } |
| 197 | |
| 198 | } |
| 199 | printk(BIOS_SPEW, "%d errors\n", errors); |
| 200 | } |
| 201 | #else |
| 202 | #define simple_spi_test() |
| 203 | #endif |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 204 | |
Arthur Heymans | a2bc254 | 2021-05-29 08:10:49 +0200 | [diff] [blame^] | 205 | #if CONFIG(SEPARATE_ROMSTAGE) |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 206 | void main(void) |
| 207 | { |
Arthur Heymans | 3e914d3 | 2022-04-06 22:25:50 +0200 | [diff] [blame] | 208 | timestamp_init(timestamp_get()); |
| 209 | timestamp_add_now(TS_ROMSTAGE_START); |
| 210 | |
| 211 | /* |
| 212 | * From the clocks comment below it looks like serial console won't |
| 213 | * work in the bootblock so keep in the romstage_main flow even with |
Arthur Heymans | a2bc254 | 2021-05-29 08:10:49 +0200 | [diff] [blame^] | 214 | * !CONFIG(SEPARATE_ROMSTAGE). |
Arthur Heymans | 3e914d3 | 2022-04-06 22:25:50 +0200 | [diff] [blame] | 215 | */ |
| 216 | romstage_main(); |
| 217 | } |
Arthur Heymans | a2bc254 | 2021-05-29 08:10:49 +0200 | [diff] [blame^] | 218 | #endif |
Arthur Heymans | 3e914d3 | 2022-04-06 22:25:50 +0200 | [diff] [blame] | 219 | |
| 220 | void __noreturn romstage_main(void) |
| 221 | { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 222 | |
| 223 | extern struct mem_timings mem_timings; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 224 | int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 225 | int power_init_failed; |
| 226 | |
Hung-Te Lin | 0682cfe | 2013-08-06 20:37:55 +0800 | [diff] [blame] | 227 | exynos5420_config_smp(); |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 228 | power_init_failed = setup_power(is_resume); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 229 | |
| 230 | /* Clock must be initialized before console_init, otherwise you may need |
| 231 | * to re-initialize serial console drivers again. */ |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 232 | system_clock_init(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 233 | |
Gabe Black | 136e709 | 2013-08-09 00:31:09 -0700 | [diff] [blame] | 234 | exynos_pinmux_uart3(); |
Stefan Reinauer | 998ab0d | 2013-05-20 12:29:37 -0700 | [diff] [blame] | 235 | console_init(); |
Julius Werner | 85620db | 2013-11-13 18:22:15 -0800 | [diff] [blame] | 236 | exception_init(); |
Stefan Reinauer | 998ab0d | 2013-05-20 12:29:37 -0700 | [diff] [blame] | 237 | |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 238 | if (power_init_failed) |
Elyes HAOUAS | 08fc8ff | 2018-08-07 12:19:10 +0200 | [diff] [blame] | 239 | die("Failed to initialize power.\n"); |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 240 | |
| 241 | /* re-initialize PMIC I2C channel after (re-)setting system clocks */ |
| 242 | i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ |
| 243 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 244 | timestamp_add_now(TS_INITRAM_START); |
Kyösti Mälkki | f48b38b | 2014-12-31 08:50:36 +0200 | [diff] [blame] | 245 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 246 | setup_memory(&mem_timings, is_resume); |
| 247 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 248 | timestamp_add_now(TS_INITRAM_END); |
Kyösti Mälkki | f48b38b | 2014-12-31 08:50:36 +0200 | [diff] [blame] | 249 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 250 | primitive_mem_test(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 251 | |
Gabe Black | 8128a56 | 2013-09-18 05:48:37 -0700 | [diff] [blame] | 252 | trustzone_init(); |
| 253 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 254 | if (is_resume) { |
| 255 | wakeup(); |
| 256 | } |
| 257 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 258 | setup_gpio(); |
Hung-Te Lin | c357aed | 2013-06-24 20:02:01 +0800 | [diff] [blame] | 259 | setup_ec(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 260 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 261 | simple_spi_test(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 262 | /* Set SPI (primary CBFS media) clock to 50MHz. */ |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 263 | /* if this is uncommented SPI will not work correctly. */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 264 | clock_set_rate(PERIPH_ID_SPI1, 50000000); |
Julius Werner | 45d2ff3 | 2013-08-12 18:04:06 -0700 | [diff] [blame] | 265 | exynos_pinmux_spi1(); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 266 | simple_spi_test(); |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 267 | |
| 268 | cbmem_initialize_empty(); |
| 269 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 270 | simple_spi_test(); |
Kyösti Mälkki | f48b38b | 2014-12-31 08:50:36 +0200 | [diff] [blame] | 271 | |
Aaron Durbin | e4f3e7a | 2015-03-17 13:25:19 -0500 | [diff] [blame] | 272 | run_ramstage(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 273 | } |