Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 4 | * Copyright 2013 Google Inc. |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <types.h> |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 21 | #include <stdlib.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 22 | |
| 23 | #include <armv7.h> |
| 24 | #include <cbfs.h> |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 25 | #include <cbmem.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 26 | |
| 27 | #include <arch/cache.h> |
| 28 | #include <cpu/samsung/exynos5420/i2c.h> |
| 29 | #include <cpu/samsung/exynos5420/clk.h> |
| 30 | #include <cpu/samsung/exynos5420/cpu.h> |
| 31 | #include <cpu/samsung/exynos5420/dmc.h> |
| 32 | #include <cpu/samsung/exynos5420/gpio.h> |
| 33 | #include <cpu/samsung/exynos5420/setup.h> |
| 34 | #include <cpu/samsung/exynos5420/periph.h> |
| 35 | #include <cpu/samsung/exynos5420/power.h> |
| 36 | #include <cpu/samsung/exynos5420/wakeup.h> |
| 37 | #include <console/console.h> |
| 38 | #include <arch/stages.h> |
| 39 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 40 | #include <drivers/maxim/max77802/max77802.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 41 | #include <device/i2c.h> |
| 42 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 43 | #define MMC0_GPIO_PIN (58) |
| 44 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 45 | struct pmic_write |
| 46 | { |
| 47 | int or_orig; // Whether to or in the original value. |
| 48 | uint8_t reg; // Register to write. |
| 49 | uint8_t val; // Value to write. |
| 50 | }; |
| 51 | |
| 52 | /* |
| 53 | * Use read-modify-write for MAX77802 control registers and clobber the |
| 54 | * output voltage setting (BUCK?DVS?) registers. |
| 55 | */ |
| 56 | struct pmic_write pmic_writes[] = |
| 57 | { |
| 58 | { 1, MAX77802_REG_PMIC_32KHZ, MAX77802_32KHCP_EN }, |
| 59 | { 0, MAX77802_REG_PMIC_BUCK1DVS1, MAX77802_BUCK1DVS1_1V }, |
| 60 | { 1, MAX77802_REG_PMIC_BUCK1CTRL, MAX77802_BUCK_TYPE1_ON | |
| 61 | MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, |
David Hendricks | 1f9f04e | 2013-08-01 18:57:52 -0700 | [diff] [blame^] | 62 | { 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1_2625V }, |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 63 | { 1, MAX77802_REG_PMIC_BUCK2CTRL1, MAX77802_BUCK_TYPE2_ON | |
| 64 | MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, |
| 65 | { 0, MAX77802_REG_PMIC_BUCK3DVS1, MAX77802_BUCK3DVS1_1V }, |
| 66 | { 1, MAX77802_REG_PMIC_BUCK3CTRL1, MAX77802_BUCK_TYPE2_ON | |
| 67 | MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, |
| 68 | { 0, MAX77802_REG_PMIC_BUCK4DVS1, MAX77802_BUCK4DVS1_1V }, |
| 69 | { 1, MAX77802_REG_PMIC_BUCK4CTRL1, MAX77802_BUCK_TYPE2_ON | |
| 70 | MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, |
| 71 | { 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V }, |
| 72 | { 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON | |
Ronald G. Minnich | 88ac9b5 | 2013-06-26 17:28:52 -0700 | [diff] [blame] | 73 | MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, |
David Hendricks | 1f9f04e | 2013-08-01 18:57:52 -0700 | [diff] [blame^] | 74 | /* Disable Boost(bypass) OUTPUT */ |
| 75 | { 0, MAX77802_REG_PMIC_BOOSTCTRL, MAX77802_BOOSTCTRL_OFF}, |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 76 | }; |
| 77 | |
Hung-Te Lin | da7b8e4 | 2013-06-28 17:27:17 +0800 | [diff] [blame] | 78 | static void setup_power(int is_resume) |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 79 | { |
| 80 | int error = 0; |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 81 | int i; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 82 | |
| 83 | power_init(); |
| 84 | |
Hung-Te Lin | da7b8e4 | 2013-06-28 17:27:17 +0800 | [diff] [blame] | 85 | if (is_resume) { |
| 86 | return; |
| 87 | } |
| 88 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 89 | /* Initialize I2C bus to configure PMIC. */ |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 90 | exynos_pinmux_i2c4(); |
Gabe Black | 925ad2e | 2013-07-31 23:21:34 -0700 | [diff] [blame] | 91 | i2c_init(4, 1000000, 0x00); /* 1MHz */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 92 | |
| 93 | printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 94 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 95 | for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { |
| 96 | uint8_t data = 0; |
| 97 | uint8_t reg = pmic_writes[i].reg; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 98 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 99 | if (pmic_writes[i].or_orig) |
| 100 | error |= i2c_read(4, MAX77802_I2C_ADDR, |
| 101 | reg, sizeof(reg), |
| 102 | &data, sizeof(data)); |
| 103 | data |= pmic_writes[i].val; |
| 104 | error |= i2c_write(4, MAX77802_I2C_ADDR, |
| 105 | reg, sizeof(reg), |
| 106 | &data, sizeof(data)); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 107 | } |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 108 | |
| 109 | if (error) |
| 110 | die("Failed to intialize PMIC.\n"); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | static void setup_storage(void) |
| 114 | { |
| 115 | /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ |
Hung-Te Lin | f6d6e62 | 2013-07-03 19:07:21 +0800 | [diff] [blame] | 116 | if (clock_set_dwmci(PERIPH_ID_SDMMC0)) |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 117 | printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__); |
Gabe Black | e6a44eb | 2013-06-15 23:40:26 -0700 | [diff] [blame] | 118 | exynos_pinmux_sdmmc0(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 119 | |
| 120 | /* MMC2: Removable, 4 bit mode, no GPIO. */ |
Hung-Te Lin | f6d6e62 | 2013-07-03 19:07:21 +0800 | [diff] [blame] | 121 | clock_set_dwmci(PERIPH_ID_SDMMC2); |
Gabe Black | e6a44eb | 2013-06-15 23:40:26 -0700 | [diff] [blame] | 122 | exynos_pinmux_sdmmc2(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 123 | } |
| 124 | |
Hung-Te Lin | c357aed | 2013-06-24 20:02:01 +0800 | [diff] [blame] | 125 | static void setup_ec(void) |
| 126 | { |
| 127 | /* SPI2 (EC) is slower and needs to work in half-duplex mode with |
| 128 | * single byte bus width. */ |
Gabe Black | 9801809 | 2013-07-24 06:18:20 -0700 | [diff] [blame] | 129 | clock_set_rate(PERIPH_ID_SPI2, 5000000); |
Hung-Te Lin | c357aed | 2013-06-24 20:02:01 +0800 | [diff] [blame] | 130 | exynos_pinmux_spi2(); |
| 131 | } |
| 132 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 133 | static void setup_gpio(void) |
| 134 | { |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 135 | gpio_direction_input(GPIO_X30); // WP_GPIO |
| 136 | gpio_set_pull(GPIO_X30, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 137 | |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 138 | gpio_direction_input(GPIO_X07); // RECMODE_GPIO |
| 139 | gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 140 | |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 141 | gpio_direction_input(GPIO_X34); // LID_GPIO |
| 142 | gpio_set_pull(GPIO_X34, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 143 | |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 144 | gpio_direction_input(GPIO_X12); // POWER_GPIO |
| 145 | gpio_set_pull(GPIO_X12, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | static void setup_memory(struct mem_timings *mem, int is_resume) |
| 149 | { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 150 | printk(BIOS_SPEW, "manufacturer: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 151 | mem->mem_manuf, |
| 152 | mem->mem_type, |
| 153 | mem->mpll_mdiv, |
| 154 | mem->frequency_mhz); |
| 155 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 156 | if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { |
| 157 | die("Failed to initialize memory controller.\n"); |
| 158 | } |
| 159 | } |
| 160 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 161 | #define PRIMITIVE_MEM_TEST 0 |
| 162 | #if PRIMITIVE_MEM_TEST |
| 163 | static unsigned long primitive_mem_test(void) |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 164 | { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 165 | unsigned long *l = (void *)0x40000000; |
| 166 | int bad = 0; |
| 167 | unsigned long i; |
| 168 | for(i = 0; i < 256*1048576; i++){ |
| 169 | if (! (i%1048576)) |
| 170 | printk(BIOS_SPEW, "%lu ...", i); |
| 171 | l[i] = 0xffffffff - i; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 172 | } |
Gabe Black | 5420e09 | 2013-05-17 11:29:22 -0700 | [diff] [blame] | 173 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 174 | for(i = 0; i < 256*1048576; i++){ |
| 175 | if (! (i%1048576)) |
| 176 | printk(BIOS_SPEW, "%lu ...", i); |
| 177 | if (l[i] != (0xffffffff - i)){ |
| 178 | printk(BIOS_SPEW, "%p: want %08lx got %08lx\n", l, l[i], 0xffffffff - i); |
| 179 | bad++; |
| 180 | } |
| 181 | } |
Gabe Black | 5420e09 | 2013-05-17 11:29:22 -0700 | [diff] [blame] | 182 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 183 | printk(BIOS_SPEW, "%d errors\n", bad); |
| 184 | |
| 185 | return bad; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 186 | } |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 187 | #else |
| 188 | #define primitive_mem_test() |
| 189 | #endif |
| 190 | |
| 191 | #define SIMPLE_SPI_TEST 0 |
| 192 | #if SIMPLE_SPI_TEST |
| 193 | /* here is a simple SPI debug test, known to fid trouble */ |
| 194 | static void simple_spi_test(void) |
| 195 | { |
| 196 | struct cbfs_media default_media, *media; |
| 197 | int i, amt = 4 * MiB, errors = 0; |
| 198 | //u32 *data = (void *)0x40000000; |
| 199 | u32 data[1024]; |
| 200 | u32 in; |
| 201 | |
| 202 | amt = sizeof(data); |
| 203 | media = &default_media; |
| 204 | if (init_default_cbfs_media(media) != 0) { |
| 205 | printk(BIOS_SPEW, "Failed to initialize default media.\n"); |
| 206 | return; |
| 207 | } |
| 208 | |
| 209 | |
| 210 | media->open(media); |
| 211 | if (media->read(media, data, (size_t) 0, amt) < amt){ |
| 212 | printk(BIOS_SPEW, "simple_spi_test fails\n"); |
| 213 | return; |
| 214 | } |
| 215 | |
| 216 | |
| 217 | for(i = 0; i < amt; i += 4){ |
| 218 | if (media->read(media, &in, (size_t) i, 4) < 1){ |
| 219 | printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); |
| 220 | return; |
| 221 | } |
| 222 | if (data[i/4] != in){ |
| 223 | errors++; |
| 224 | printk(BIOS_SPEW, "BAD at %d(%p):\nRAM %08lx\nSPI %08lx\n", |
| 225 | i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); |
| 226 | /* reread it to see which is wrong. */ |
| 227 | if (media->read(media, &in, (size_t) i, 4) < 1){ |
| 228 | printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); |
| 229 | return; |
| 230 | } |
| 231 | printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n", |
| 232 | i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); |
| 233 | } |
| 234 | |
| 235 | } |
| 236 | printk(BIOS_SPEW, "%d errors\n", errors); |
| 237 | } |
| 238 | #else |
| 239 | #define simple_spi_test() |
| 240 | #endif |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 241 | |
| 242 | void main(void) |
| 243 | { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 244 | |
| 245 | extern struct mem_timings mem_timings; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 246 | void *entry; |
| 247 | int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); |
| 248 | |
| 249 | /* Clock must be initialized before console_init, otherwise you may need |
| 250 | * to re-initialize serial console drivers again. */ |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 251 | system_clock_init(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 252 | |
Stefan Reinauer | 998ab0d | 2013-05-20 12:29:37 -0700 | [diff] [blame] | 253 | console_init(); |
| 254 | |
Hung-Te Lin | da7b8e4 | 2013-06-28 17:27:17 +0800 | [diff] [blame] | 255 | setup_power(is_resume); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 256 | setup_memory(&mem_timings, is_resume); |
| 257 | |
| 258 | primitive_mem_test(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 259 | |
| 260 | if (is_resume) { |
| 261 | wakeup(); |
| 262 | } |
| 263 | |
| 264 | setup_storage(); |
| 265 | setup_gpio(); |
Hung-Te Lin | c357aed | 2013-06-24 20:02:01 +0800 | [diff] [blame] | 266 | setup_ec(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 267 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 268 | simple_spi_test(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 269 | /* Set SPI (primary CBFS media) clock to 50MHz. */ |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 270 | /* if this is uncommented SPI will not work correctly. */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 271 | clock_set_rate(PERIPH_ID_SPI1, 50000000); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 272 | simple_spi_test(); |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 273 | |
| 274 | cbmem_initialize_empty(); |
| 275 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 276 | entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 277 | simple_spi_test(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 278 | stage_exit(entry); |
| 279 | } |