Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 2 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
| 7 | #include <acpi/acpi_ivrs.h> |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Elyes HAOUAS | 146d0c2 | 2020-07-22 11:47:08 +0200 | [diff] [blame] | 9 | #include <types.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 13 | #include <string.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 14 | #include <stdlib.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 15 | #include <lib.h> |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 16 | #include <cpu/x86/mp.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 17 | #include <Porting.h> |
| 18 | #include <AGESA.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 19 | #include <Topology.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 20 | #include <cpu/x86/lapic.h> |
| 21 | #include <cpu/amd/msr.h> |
| 22 | #include <cpu/amd/mtrr.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 23 | #include <acpi/acpigen.h> |
Angel Pons | ec5cf15 | 2020-11-10 20:42:07 +0100 | [diff] [blame] | 24 | #include <northbridge/amd/nb_common.h> |
Kyösti Mälkki | ed8d277 | 2017-07-15 17:12:44 +0300 | [diff] [blame] | 25 | #include <northbridge/amd/agesa/agesa_helper.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 26 | #include <southbridge/amd/pi/hudson/pci_devs.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 27 | |
Kyösti Mälkki | 113f670 | 2018-05-20 20:12:32 +0300 | [diff] [blame] | 28 | #define MAX_NODE_NUMS MAX_NODES |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 29 | #define PCIE_CAP_AER BIT(5) |
| 30 | #define PCIE_CAP_ACS BIT(6) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 31 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 32 | static struct device *__f0_dev[MAX_NODE_NUMS]; |
| 33 | static struct device *__f1_dev[MAX_NODE_NUMS]; |
| 34 | static struct device *__f2_dev[MAX_NODE_NUMS]; |
| 35 | static struct device *__f4_dev[MAX_NODE_NUMS]; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 36 | static unsigned int fx_devs = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 37 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 38 | static struct device *get_node_pci(u32 nodeid, u32 fn) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 39 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 40 | return pcidev_on_root(DEV_CDB + nodeid, fn); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 41 | } |
| 42 | |
Michał Kopeć | ca1e8aa | 2021-12-03 15:17:46 +0100 | [diff] [blame] | 43 | static struct device *get_mc_dev(void) |
| 44 | { |
| 45 | return pcidev_on_root(DEV_CDB, 0); |
| 46 | } |
| 47 | |
| 48 | static unsigned int get_node_nums(void) |
| 49 | { |
| 50 | static unsigned int node_nums; |
| 51 | |
| 52 | if (node_nums) |
| 53 | return node_nums; |
| 54 | |
| 55 | node_nums = ((pci_read_config32(get_mc_dev(), 0x60)>>4) & 7) + 1; //NodeCnt[2:0] |
| 56 | |
| 57 | return node_nums; |
| 58 | } |
| 59 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 60 | static void get_fx_devs(void) |
| 61 | { |
| 62 | int i; |
| 63 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 64 | __f0_dev[i] = get_node_pci(i, 0); |
| 65 | __f1_dev[i] = get_node_pci(i, 1); |
| 66 | __f2_dev[i] = get_node_pci(i, 2); |
| 67 | __f4_dev[i] = get_node_pci(i, 4); |
| 68 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
| 69 | fx_devs = i+1; |
| 70 | } |
| 71 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 72 | die("Cannot find 0:0x18.[0|1]\n"); |
| 73 | } |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 74 | printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 75 | } |
| 76 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 77 | static void f1_write_config32(unsigned int reg, u32 value) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 78 | { |
| 79 | int i; |
| 80 | if (fx_devs == 0) |
| 81 | get_fx_devs(); |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 82 | for (i = 0; i < fx_devs; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 83 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 84 | dev = __f1_dev[i]; |
| 85 | if (dev && dev->enabled) { |
| 86 | pci_write_config32(dev, reg, value); |
| 87 | } |
| 88 | } |
| 89 | } |
| 90 | |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 91 | static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) |
| 92 | { |
| 93 | u32 temp; |
| 94 | |
| 95 | if (fx_devs == 0) |
| 96 | get_fx_devs(); |
| 97 | |
| 98 | |
| 99 | temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 100 | if (!(temp & 1)) |
| 101 | return 0; // this memory range is not enabled |
| 102 | /* |
| 103 | * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits |
| 104 | * for physical address and the convert to KiB by shifting 10 bits left |
| 105 | */ |
| 106 | *basek = ((temp & 0xffff0000)) >> (10 - 8); |
| 107 | /* |
| 108 | * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but |
| 109 | * ORed with 0xffff to get real limit before shifting. |
| 110 | */ |
| 111 | temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 112 | *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); |
| 113 | *limitk += 1; // round up last byte |
| 114 | |
| 115 | return 1; |
| 116 | } |
| 117 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 118 | static u32 amdfam16_nodeid(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 119 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 120 | return (dev->path.pci.devfn >> 3) - DEV_CDB; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 124 | { |
| 125 | u32 val; |
| 126 | |
| 127 | val = 1 | (nodeid<<4) | (linkn<<12); |
| 128 | /* it will routing |
| 129 | * (1)mmio 0xa0000:0xbffff |
| 130 | * (2)io 0x3b0:0x3bb, 0x3c0:0x3df |
| 131 | */ |
| 132 | f1_write_config32(0xf4, val); |
| 133 | |
| 134 | } |
| 135 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 136 | static void add_fixed_resources(struct device *dev, int index) |
| 137 | { |
| 138 | /* Reserve everything between A segment and 1MB: |
| 139 | * |
| 140 | * 0xa0000 - 0xbffff: legacy VGA |
| 141 | * 0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used) |
| 142 | */ |
| 143 | mmio_resource(dev, index++, 0xa0000 >> 10, (0xc0000 - 0xa0000) >> 10); |
| 144 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); |
| 145 | |
| 146 | if (fx_devs == 0) |
| 147 | get_fx_devs(); |
| 148 | |
| 149 | /* Check if CC6 save area is enabled (bit 18 CC6SaveEn) */ |
| 150 | if (pci_read_config32(__f2_dev[0], 0x118) & (1 << 18)) { |
| 151 | /* Add CC6 DRAM UC resource residing at DRAM Limit of size 16MB as per BKDG */ |
| 152 | resource_t basek, limitk; |
| 153 | if (!get_dram_base_limit(0, &basek, &limitk)) |
| 154 | return; |
| 155 | mmio_resource(dev, index++, limitk, 16*1024); |
| 156 | } |
| 157 | } |
| 158 | |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 159 | static void nb_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 160 | { |
| 161 | struct resource *res; |
Kyösti Mälkki | 5d49038 | 2015-05-27 07:58:22 +0300 | [diff] [blame] | 162 | |
| 163 | /* |
| 164 | * This MMCONF resource must be reserved in the PCI domain. |
| 165 | * It is not honored by the coreboot resource allocator if it is in |
| 166 | * the CPU_CLUSTER. |
| 167 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 168 | mmconf_resource(dev, MMIO_CONF_BASE); |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 169 | |
| 170 | /* NB IOAPIC2 resource */ |
| 171 | res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ |
| 172 | res->base = IO_APIC2_ADDR; |
| 173 | res->size = 0x00001000; |
| 174 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 175 | |
| 176 | add_fixed_resources(dev, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 177 | } |
| 178 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 179 | static void create_vga_resource(struct device *dev, unsigned int nodeid) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 180 | { |
| 181 | struct bus *link; |
Michał Kopeć | ca1e8aa | 2021-12-03 15:17:46 +0100 | [diff] [blame] | 182 | unsigned int sblink; |
| 183 | |
| 184 | sblink = (pci_read_config32(get_mc_dev(), 0x64)>>8) & 7; // don't forget sublink1 |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 185 | |
| 186 | /* find out which link the VGA card is connected, |
| 187 | * we only deal with the 'first' vga card */ |
| 188 | for (link = dev->link_list; link; link = link->next) { |
| 189 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 190 | #if CONFIG(MULTIPLE_VGA_ADAPTERS) |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 191 | extern struct device *vga_pri; // the primary vga device, defined in device.c |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 192 | printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, |
| 193 | link->secondary,link->subordinate); |
| 194 | /* We need to make sure the vga_pri is under the link */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 195 | if ((vga_pri->bus->secondary >= link->secondary) && |
| 196 | (vga_pri->bus->secondary <= link->subordinate)) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 197 | #endif |
| 198 | break; |
| 199 | } |
| 200 | } |
| 201 | |
| 202 | /* no VGA card installed */ |
| 203 | if (link == NULL) |
| 204 | return; |
| 205 | |
| 206 | printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); |
| 207 | set_vga_enable_reg(nodeid, sblink); |
| 208 | } |
| 209 | |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 210 | static void nb_set_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 211 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 212 | unsigned int nodeid; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 213 | |
| 214 | /* Find the nodeid */ |
| 215 | nodeid = amdfam16_nodeid(dev); |
| 216 | |
| 217 | create_vga_resource(dev, nodeid); //TODO: do we need this? |
| 218 | |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 219 | pci_dev_set_resources(dev); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 220 | } |
| 221 | |
| 222 | static void northbridge_init(struct device *dev) |
| 223 | { |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 224 | setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 225 | } |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 226 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 227 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 228 | { |
| 229 | void *addr, *current; |
| 230 | |
| 231 | /* Skip the HEST header. */ |
| 232 | current = (void *)(hest + 1); |
| 233 | |
| 234 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 235 | if (addr != NULL) |
| 236 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 237 | |
| 238 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 239 | if (addr != NULL) |
| 240 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 241 | |
| 242 | return (unsigned long)current; |
| 243 | } |
| 244 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 245 | unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 246 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 247 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 248 | current = ALIGN_UP(current, 8); |
| 249 | ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 250 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 251 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 252 | ivhd_ioapic->reserved = 0x0000; |
| 253 | ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 254 | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | |
| 255 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; |
| 256 | ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ |
| 257 | ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 258 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 259 | current += sizeof(ivrs_ivhd_special_t); |
| 260 | |
| 261 | ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
| 262 | |
| 263 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 264 | ivhd_ioapic->reserved = 0x0000; |
| 265 | ivhd_ioapic->dte_setting = 0x00; |
| 266 | ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ |
| 267 | ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); |
| 268 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 269 | current += sizeof(ivrs_ivhd_special_t); |
| 270 | |
| 271 | return current; |
| 272 | } |
| 273 | |
| 274 | static unsigned long ivhd_describe_hpet(unsigned long current) |
| 275 | { |
| 276 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 277 | current = ALIGN_UP(current, 8); |
| 278 | ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; |
| 279 | |
| 280 | ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 281 | ivhd_hpet->reserved = 0x0000; |
| 282 | ivhd_hpet->dte_setting = 0x00; |
| 283 | ivhd_hpet->handle = 0x00; |
| 284 | ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 285 | ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; |
| 286 | current += sizeof(ivrs_ivhd_special_t); |
| 287 | |
| 288 | return current; |
| 289 | } |
| 290 | |
| 291 | static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, |
| 292 | uint16_t end_devid, uint8_t setting) |
| 293 | { |
| 294 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 295 | current = ALIGN_UP(current, 4); |
| 296 | ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 297 | |
| 298 | /* Create the start range IVHD entry */ |
| 299 | ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; |
| 300 | ivhd_range->dev_id = start_devid; |
| 301 | ivhd_range->dte_setting = setting; |
| 302 | current += sizeof(ivrs_ivhd_generic_t); |
| 303 | |
| 304 | /* Create the end range IVHD entry */ |
| 305 | ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 306 | ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; |
| 307 | ivhd_range->dev_id = end_devid; |
| 308 | ivhd_range->dte_setting = setting; |
| 309 | current += sizeof(ivrs_ivhd_generic_t); |
| 310 | |
| 311 | return current; |
| 312 | } |
| 313 | |
| 314 | static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, |
| 315 | unsigned long *current, uint8_t type, uint8_t data) |
| 316 | { |
| 317 | if (type == IVHD_DEV_4_BYTE_SELECT) { |
| 318 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 319 | *current = ALIGN_UP(*current, 4); |
| 320 | ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; |
| 321 | |
| 322 | ivhd_entry->type = type; |
| 323 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 324 | ivhd_entry->dte_setting = data; |
| 325 | *current += sizeof(ivrs_ivhd_generic_t); |
| 326 | } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { |
| 327 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 328 | *current = ALIGN_UP(*current, 8); |
| 329 | ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; |
| 330 | |
| 331 | ivhd_entry->type = type; |
| 332 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 333 | ivhd_entry->dte_setting = data; |
| 334 | ivhd_entry->reserved1 = 0; |
| 335 | ivhd_entry->reserved2 = 0; |
| 336 | ivhd_entry->source_dev_id = parent->path.pci.devfn | |
| 337 | (parent->bus->secondary << 8); |
| 338 | *current += sizeof(ivrs_ivhd_alias_t); |
| 339 | } |
| 340 | |
| 341 | return *current; |
| 342 | } |
| 343 | |
| 344 | static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, |
| 345 | unsigned long *current, uint16_t *ivhd_length) |
| 346 | { |
| 347 | unsigned int header_type, is_pcie; |
| 348 | unsigned long current_backup; |
| 349 | |
| 350 | header_type = dev->hdr_type & 0x7f; |
| 351 | is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 352 | |
| 353 | if (((header_type == PCI_HEADER_TYPE_NORMAL) || |
| 354 | (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { |
| 355 | /* Device or Bridge is PCIe */ |
| 356 | current_backup = *current; |
| 357 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); |
| 358 | *ivhd_length += (*current - current_backup); |
| 359 | } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { |
| 360 | /* Device is legacy PCI or PCI-X */ |
| 361 | current_backup = *current; |
| 362 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); |
| 363 | *ivhd_length += (*current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 364 | } |
| 365 | } |
| 366 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 367 | static void add_ivhd_device_entries(struct device *parent, struct device *dev, |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 368 | unsigned int depth, int linknum, int8_t *root_level, |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 369 | unsigned long *current, uint16_t *ivhd_length) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 370 | { |
| 371 | struct device *sibling; |
| 372 | struct bus *link; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 373 | |
| 374 | if (!root_level) { |
| 375 | root_level = malloc(sizeof(int8_t)); |
| 376 | *root_level = -1; |
| 377 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 378 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 379 | if (dev->path.type == DEVICE_PATH_PCI) { |
| 380 | |
| 381 | if ((dev->bus->secondary == 0x0) && |
| 382 | (dev->path.pci.devfn == 0x0)) |
| 383 | *root_level = depth; |
| 384 | |
| 385 | if ((*root_level != -1) && (dev->enabled)) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 386 | if (depth != *root_level) |
| 387 | ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 388 | } |
| 389 | } |
| 390 | |
| 391 | for (link = dev->link_list; link; link = link->next) |
| 392 | for (sibling = link->children; sibling; sibling = |
| 393 | sibling->sibling) |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 394 | add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, |
| 395 | current, ivhd_length); |
| 396 | |
| 397 | free(root_level); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 398 | } |
| 399 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 400 | #define IOMMU_MMIO32(x) (*((volatile uint32_t *)(x))) |
| 401 | #define EFR_SUPPORT BIT(27) |
| 402 | |
| 403 | static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_agesa) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 404 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 405 | acpi_ivrs_ivhd11_t *ivhd_11; |
| 406 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 407 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 408 | /* |
| 409 | * These devices should be already found by previous function. |
| 410 | * Do not perform NULL checks. |
| 411 | */ |
| 412 | struct device *nb_dev = pcidev_on_root(0, 0); |
| 413 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 414 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 415 | /* |
| 416 | * In order to utilize all features, firmware should expose type 11h |
| 417 | * IVHD which supersedes the type 10h. |
| 418 | */ |
| 419 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); |
| 420 | ivhd_11 = (acpi_ivrs_ivhd11_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 421 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 422 | /* Enable EFR */ |
| 423 | ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; |
| 424 | /* For type 11h bits 6 and 7 are reserved */ |
| 425 | ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; |
| 426 | ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); |
| 427 | /* BDF <bus>:00.2 */ |
| 428 | ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 429 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
| 430 | ivhd_11->capability_offset = 0x40; |
| 431 | ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 432 | ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
| 433 | ivhd_11->pci_segment_group = 0x0000; |
| 434 | ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 435 | ivhd_11->iommu_attributes.perf_counters = |
| 436 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf; |
| 437 | ivhd_11->iommu_attributes.perf_counter_banks = |
| 438 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 12) & 0x3f; |
| 439 | ivhd_11->iommu_attributes.msi_num_ppr = |
| 440 | (pci_read_config32(iommu_dev, ivhd_11->capability_offset + 0x10) >> 27) & 0x1f; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 441 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 442 | if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_SUPPORT) { |
| 443 | ivhd_11->efr_reg_image_low = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x30); |
| 444 | ivhd_11->efr_reg_image_high = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x34); |
| 445 | } |
| 446 | |
| 447 | current += sizeof(acpi_ivrs_ivhd11_t); |
| 448 | |
| 449 | /* Now repeat all the device entries from type 10h */ |
| 450 | current_backup = current; |
| 451 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 452 | ivhd_11->length += (current - current_backup); |
| 453 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivhd_11->length); |
| 454 | |
| 455 | /* Describe HPET */ |
| 456 | current_backup = current; |
| 457 | current = ivhd_describe_hpet(current); |
| 458 | ivhd_11->length += (current - current_backup); |
| 459 | |
| 460 | /* Describe IOAPICs */ |
| 461 | current_backup = current; |
| 462 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 463 | ivhd_11->length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 464 | |
| 465 | return current; |
| 466 | } |
| 467 | |
| 468 | static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) |
| 469 | { |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 470 | acpi_ivrs_t *ivrs_agesa; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 471 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 472 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 473 | struct device *nb_dev = pcidev_on_root(0, 0); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 474 | if (!nb_dev) { |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 475 | printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); |
| 476 | printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); |
| 477 | |
| 478 | return (unsigned long)ivrs; |
| 479 | } |
| 480 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 481 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 482 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 483 | if (!iommu_dev) { |
| 484 | printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); |
| 485 | |
| 486 | return (unsigned long)ivrs; |
| 487 | } |
| 488 | |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 489 | ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); |
| 490 | if (ivrs_agesa != NULL) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 491 | ivrs->iv_info = ivrs_agesa->iv_info; |
| 492 | ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; |
| 493 | ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 494 | ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); |
| 495 | /* BDF <bus>:00.2 */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 496 | ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 497 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 498 | ivrs->ivhd.capability_offset = 0x40; |
| 499 | ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 500 | ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 501 | ivrs->ivhd.pci_segment_group = 0x0000; |
| 502 | ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 503 | ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info; |
| 504 | /* Enable EFR if supported */ |
| 505 | if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) |
| 506 | ivrs->iv_info |= IVINFO_EFR_SUPPORTED; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 507 | } else { |
| 508 | printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); |
| 509 | |
| 510 | return (unsigned long)ivrs; |
| 511 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 512 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 513 | /* |
| 514 | * Add all possible PCI devices on bus 0 that can generate transactions |
| 515 | * processed by IOMMU. Start with device 00:01.0 since IOMMU does not |
| 516 | * translate transactions generated by itself. |
| 517 | */ |
| 518 | current_backup = current; |
| 519 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 520 | ivrs->ivhd.length += (current - current_backup); |
| 521 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 522 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 523 | /* Describe HPET */ |
| 524 | current_backup = current; |
| 525 | current = ivhd_describe_hpet(current); |
| 526 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 527 | |
| 528 | /* Describe IOAPICs */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 529 | current_backup = current; |
| 530 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 531 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 532 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 533 | /* If EFR is not supported, IVHD type 11h is reserved */ |
| 534 | if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) |
| 535 | return current; |
| 536 | |
| 537 | return acpi_fill_ivrs11(current, ivrs_agesa); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 538 | } |
| 539 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 540 | static void northbridge_fill_ssdt_generator(const struct device *device) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 541 | { |
| 542 | msr_t msr; |
| 543 | char pscope[] = "\\_SB.PCI0"; |
| 544 | |
| 545 | acpigen_write_scope(pscope); |
| 546 | msr = rdmsr(TOP_MEM); |
| 547 | acpigen_write_name_dword("TOM1", msr.lo); |
| 548 | msr = rdmsr(TOP_MEM2); |
| 549 | /* |
| 550 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 551 | * here. |
| 552 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 553 | * slide 22ff. |
| 554 | * Shift value right by 20 bit to make it fit into 32bit, |
| 555 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 556 | */ |
| 557 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 558 | acpigen_pop_len(); |
| 559 | } |
| 560 | |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 561 | static void patch_ssdt_processor_scope(acpi_header_t *ssdt) |
| 562 | { |
| 563 | unsigned int len = ssdt->length - sizeof(acpi_header_t); |
| 564 | unsigned int i; |
| 565 | |
| 566 | for (i = sizeof(acpi_header_t); i < len; i++) { |
| 567 | /* Search for _PR_ scope and replace it with _SB_ */ |
| 568 | if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) |
| 569 | *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; |
| 570 | } |
| 571 | /* Recalculate checksum */ |
| 572 | ssdt->checksum = 0; |
| 573 | ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); |
| 574 | } |
| 575 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 576 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 577 | unsigned long current, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 578 | acpi_rsdp_t *rsdp) |
| 579 | { |
| 580 | acpi_srat_t *srat; |
| 581 | acpi_slit_t *slit; |
| 582 | acpi_header_t *ssdt; |
| 583 | acpi_header_t *alib; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 584 | acpi_ivrs_t *ivrs; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 585 | |
| 586 | /* HEST */ |
| 587 | current = ALIGN(current, 8); |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 588 | acpi_write_hest((void *)current, acpi_fill_hest); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 589 | acpi_add_table(rsdp, (void *)current); |
| 590 | current += ((acpi_header_t *)current)->length; |
| 591 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 592 | /* IVRS */ |
| 593 | current = ALIGN(current, 8); |
| 594 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 595 | ivrs = (acpi_ivrs_t *) current; |
| 596 | acpi_create_ivrs(ivrs, acpi_fill_ivrs); |
| 597 | current += ivrs->header.length; |
| 598 | acpi_add_table(rsdp, ivrs); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 599 | |
| 600 | /* SRAT */ |
| 601 | current = ALIGN(current, 8); |
| 602 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 603 | srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); |
| 604 | if (srat != NULL) { |
| 605 | memcpy((void *)current, srat, srat->header.length); |
| 606 | srat = (acpi_srat_t *) current; |
| 607 | current += srat->header.length; |
| 608 | acpi_add_table(rsdp, srat); |
| 609 | } else { |
| 610 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 611 | } |
| 612 | |
| 613 | /* SLIT */ |
| 614 | current = ALIGN(current, 8); |
| 615 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 616 | slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); |
| 617 | if (slit != NULL) { |
| 618 | memcpy((void *)current, slit, slit->header.length); |
| 619 | slit = (acpi_slit_t *) current; |
| 620 | current += slit->header.length; |
| 621 | acpi_add_table(rsdp, slit); |
| 622 | } else { |
| 623 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 624 | } |
| 625 | |
| 626 | /* ALIB */ |
| 627 | current = ALIGN(current, 16); |
| 628 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
| 629 | alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); |
| 630 | if (alib != NULL) { |
| 631 | memcpy((void *)current, alib, alib->length); |
| 632 | alib = (acpi_header_t *) current; |
| 633 | current += alib->length; |
| 634 | acpi_add_table(rsdp, (void *)alib); |
| 635 | } |
| 636 | else { |
| 637 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 638 | } |
| 639 | |
| 640 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 641 | /* SSDT */ |
| 642 | current = ALIGN(current, 16); |
| 643 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
| 644 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); |
| 645 | if (ssdt != NULL) { |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 646 | patch_ssdt_processor_scope(ssdt); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 647 | memcpy((void *)current, ssdt, ssdt->length); |
| 648 | ssdt = (acpi_header_t *) current; |
| 649 | current += ssdt->length; |
| 650 | } |
| 651 | else { |
| 652 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 653 | } |
| 654 | acpi_add_table(rsdp,ssdt); |
| 655 | |
| 656 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 657 | return current; |
| 658 | } |
| 659 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 660 | static struct device_operations northbridge_operations = { |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 661 | .read_resources = nb_read_resources, |
| 662 | .set_resources = nb_set_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 663 | .enable_resources = pci_dev_enable_resources, |
| 664 | .init = northbridge_init, |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 665 | .ops_pci = &pci_dev_ops_pci, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 666 | .acpi_fill_ssdt = northbridge_fill_ssdt_generator, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 667 | .write_acpi_tables = agesa_write_acpi_tables, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 668 | }; |
| 669 | |
| 670 | static const struct pci_driver family16_northbridge __pci_driver = { |
| 671 | .ops = &northbridge_operations, |
| 672 | .vendor = PCI_VENDOR_ID_AMD, |
Marshall Dawson | 463f46e | 2016-10-14 20:46:08 -0600 | [diff] [blame] | 673 | .device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 674 | }; |
| 675 | |
| 676 | static const struct pci_driver family10_northbridge __pci_driver = { |
| 677 | .ops = &northbridge_operations, |
| 678 | .vendor = PCI_VENDOR_ID_AMD, |
| 679 | .device = PCI_DEVICE_ID_AMD_10H_NB_HT, |
| 680 | }; |
| 681 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 682 | static void fam16_finalize(void *chip_info) |
| 683 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 684 | struct device *dev; |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 685 | u32 value; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 686 | dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 687 | pci_write_config32(dev, 0xF8, 0); |
| 688 | pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ |
| 689 | |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 690 | /* |
| 691 | * Currently it is impossible to enable ACS with AGESA by setting the |
| 692 | * correct bit for AmdInitMid phase. AGESA code path does not call the |
| 693 | * right function that enables these functionalities. Disabled ACS |
| 694 | * result in multiple PCIe devices to be assigned to the same IOMMU |
| 695 | * group. Without IOMMU group separation the devices cannot be passed |
| 696 | * through independently. |
| 697 | */ |
| 698 | |
| 699 | /* Select GPP link core IO Link Strap Control register 0xB0 */ |
| 700 | pci_write_config32(dev, 0xE0, 0x014000B0); |
| 701 | value = pci_read_config32(dev, 0xE4); |
| 702 | |
| 703 | /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ |
| 704 | value |= PCIE_CAP_AER | PCIE_CAP_ACS; |
| 705 | pci_write_config32(dev, 0xE4, value); |
| 706 | |
| 707 | /* Select GPP link core Wrapper register 0x00 (undocumented) */ |
| 708 | pci_write_config32(dev, 0xE0, 0x01300000); |
| 709 | value = pci_read_config32(dev, 0xE4); |
| 710 | |
| 711 | /* |
| 712 | * Enable ACS capabilities straps including sub-items. From lspci it |
| 713 | * looks like these bits enable: Source Validation and Translation |
| 714 | * Blocking |
| 715 | */ |
| 716 | value |= (BIT(24) | BIT(25) | BIT(26)); |
| 717 | pci_write_config32(dev, 0xE4, value); |
| 718 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 719 | /* disable No Snoop */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 720 | dev = pcidev_on_root(1, 1); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 721 | if (dev != NULL) { |
| 722 | value = pci_read_config32(dev, 0x60); |
| 723 | value &= ~(1 << 11); |
| 724 | pci_write_config32(dev, 0x60, value); |
| 725 | } |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 726 | } |
| 727 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 728 | struct chip_operations northbridge_amd_pi_00730F01_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 729 | CHIP_NAME("AMD FAM16 Northbridge") |
| 730 | .enable_dev = 0, |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 731 | .final = fam16_finalize, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 732 | }; |
| 733 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 734 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 735 | struct hw_mem_hole_info { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 736 | unsigned int hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 737 | int node_id; |
| 738 | }; |
| 739 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 740 | { |
| 741 | struct hw_mem_hole_info mem_hole; |
| 742 | int i; |
| 743 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 744 | mem_hole.node_id = -1; |
Michał Kopeć | ca1e8aa | 2021-12-03 15:17:46 +0100 | [diff] [blame] | 745 | for (i = 0; i < get_node_nums(); i++) { |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 746 | resource_t basek, limitk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 747 | u32 hole; |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 748 | if (!get_dram_base_limit(i, &basek, &limitk)) |
| 749 | continue; // no memory on this node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 750 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 751 | if (hole & 2) { // we find the hole |
| 752 | mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; |
| 753 | mem_hole.node_id = i; // record the node No with hole |
| 754 | break; // only one hole |
| 755 | } |
| 756 | } |
| 757 | |
| 758 | /* We need to double check if there is special set on base reg and limit reg |
| 759 | * are not continuous instead of hole, it will find out its hole_startk. |
| 760 | */ |
| 761 | if (mem_hole.node_id == -1) { |
| 762 | resource_t limitk_pri = 0; |
Michał Kopeć | ca1e8aa | 2021-12-03 15:17:46 +0100 | [diff] [blame] | 763 | for (i = 0; i < get_node_nums(); i++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 764 | resource_t base_k, limit_k; |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 765 | if (!get_dram_base_limit(i, &base_k, &limit_k)) |
| 766 | continue; // no memory on this node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 767 | if (base_k > 4 *1024 * 1024) break; // don't need to go to check |
| 768 | if (limitk_pri != base_k) { // we find the hole |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 769 | mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 770 | mem_hole.node_id = i; |
| 771 | break; //only one hole |
| 772 | } |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 773 | limitk_pri = limit_k; |
| 774 | } |
| 775 | } |
| 776 | return mem_hole; |
| 777 | } |
| 778 | #endif |
| 779 | |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 780 | static void domain_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 781 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 782 | unsigned long mmio_basek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 783 | int i, idx; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 784 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 785 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 786 | #endif |
| 787 | |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 788 | pci_domain_read_resources(dev); |
| 789 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 790 | /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ |
Arthur Heymans | c435038 | 2021-10-28 12:35:39 +0200 | [diff] [blame] | 791 | mmio_basek = amd_topmem() >> 10; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 792 | |
| 793 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 794 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 795 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 796 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 797 | * otherwise We reset the hole to the mmio_basek |
| 798 | */ |
| 799 | |
| 800 | mem_hole = get_hw_mem_hole_info(); |
| 801 | |
| 802 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 803 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 804 | mmio_basek = mem_hole.hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 805 | } |
| 806 | #endif |
| 807 | |
| 808 | idx = 0x10; |
Michał Kopeć | ca1e8aa | 2021-12-03 15:17:46 +0100 | [diff] [blame] | 809 | for (i = 0; i < get_node_nums(); i++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 810 | resource_t basek, limitk, sizek; // 4 1T |
| 811 | |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 812 | if (!get_dram_base_limit(i, &basek, &limitk)) |
| 813 | continue; // no memory on this node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 814 | |
| 815 | sizek = limitk - basek; |
| 816 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 817 | printk(BIOS_DEBUG, "node %d: basek=%08llx, limitk=%08llx, sizek=%08llx,\n", |
| 818 | i, basek, limitk, sizek); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 819 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 820 | /* see if we need a hole from 0xa0000 to 0xfffff */ |
| 821 | if ((basek < (0xa0000 >> 10) && (sizek > (0x100000 >> 10)))) { |
| 822 | ram_resource(dev, (idx | i), basek, (0xa0000 >> 10) - basek); |
| 823 | idx += 0x10; |
| 824 | basek = 0x100000 >> 10; |
| 825 | sizek = limitk - basek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 826 | } |
| 827 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 828 | printk(BIOS_DEBUG, "node %d: basek=%08llx, limitk=%08llx, sizek=%08llx,\n", |
| 829 | i, basek, limitk, sizek); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 830 | |
| 831 | /* split the region to accommodate pci memory space */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 832 | if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 833 | if (basek <= mmio_basek) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 834 | unsigned int pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 835 | pre_sizek = mmio_basek - basek; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 836 | if (pre_sizek > 0) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 837 | ram_resource(dev, (idx | i), basek, pre_sizek); |
| 838 | idx += 0x10; |
| 839 | sizek -= pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 840 | } |
| 841 | basek = mmio_basek; |
| 842 | } |
| 843 | if ((basek + sizek) <= 4*1024*1024) { |
| 844 | sizek = 0; |
| 845 | } |
| 846 | else { |
Arthur Heymans | c435038 | 2021-10-28 12:35:39 +0200 | [diff] [blame] | 847 | uint64_t topmem2 = amd_topmem2(); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 848 | basek = 4*1024*1024; |
| 849 | sizek = topmem2/1024 - basek; |
| 850 | } |
| 851 | } |
| 852 | |
| 853 | ram_resource(dev, (idx | i), basek, sizek); |
| 854 | idx += 0x10; |
| 855 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 856 | i, mmio_basek, basek, limitk); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 857 | } |
| 858 | |
Kyösti Mälkki | e87564f | 2017-04-15 20:07:53 +0300 | [diff] [blame] | 859 | add_uma_resource_below_tolm(dev, 7); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 860 | } |
| 861 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 862 | static const char *domain_acpi_name(const struct device *dev) |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 863 | { |
| 864 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 865 | return "PCI0"; |
| 866 | |
| 867 | return NULL; |
| 868 | } |
| 869 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 870 | static struct device_operations pci_domain_ops = { |
| 871 | .read_resources = domain_read_resources, |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 872 | .set_resources = pci_domain_set_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 873 | .scan_bus = pci_domain_scan_bus, |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 874 | .acpi_name = domain_acpi_name, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 875 | }; |
| 876 | |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 877 | static void pre_mp_init(void) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 878 | { |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 879 | x86_setup_mtrrs_with_detect(); |
| 880 | x86_mtrr_check(); |
| 881 | } |
| 882 | |
| 883 | static int get_cpu_count(void) |
| 884 | { |
| 885 | uint8_t siblings = cpuid_ecx(0x80000008) & 0xff; |
| 886 | |
| 887 | return siblings + 1; |
| 888 | } |
| 889 | |
| 890 | static const struct mp_ops mp_ops = { |
| 891 | .pre_mp_init = pre_mp_init, |
| 892 | .get_cpu_count = get_cpu_count, |
| 893 | }; |
| 894 | |
| 895 | void mp_init_cpus(struct bus *cpu_bus) |
| 896 | { |
| 897 | /* TODO: Handle mp_init_with_smm failure? */ |
| 898 | mp_init_with_smm(cpu_bus, &mp_ops); |
| 899 | |
| 900 | /* The flash is now no longer cacheable. Reset to WP for performance. */ |
| 901 | mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, |
| 902 | MTRR_TYPE_WRPROT); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 903 | } |
| 904 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 905 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 906 | .read_resources = noop_read_resources, |
| 907 | .set_resources = noop_set_resources, |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 908 | .init = mp_cpu_bus_init, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 909 | }; |
| 910 | |
| 911 | static void root_complex_enable_dev(struct device *dev) |
| 912 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 913 | /* Set the operations if it is a special bus type */ |
| 914 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 915 | dev->ops = &pci_domain_ops; |
| 916 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 917 | dev->ops = &cpu_bus_ops; |
| 918 | } |
| 919 | } |
| 920 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 921 | struct chip_operations northbridge_amd_pi_00730F01_root_complex_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 922 | CHIP_NAME("AMD FAM16 Root Complex") |
| 923 | .enable_dev = root_complex_enable_dev, |
| 924 | }; |
| 925 | |
| 926 | /********************************************************************* |
| 927 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 928 | *********************************************************************/ |
| 929 | u32 map_oprom_vendev(u32 vendev) |
| 930 | { |
| 931 | u32 new_vendev; |
| 932 | new_vendev = |
| 933 | ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; |
| 934 | |
| 935 | if (vendev != new_vendev) |
| 936 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 937 | |
| 938 | return new_vendev; |
| 939 | } |