Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ALDERLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Alderlake support |
| 5 | |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 6 | config SOC_INTEL_ALDERLAKE_PCH_M |
| 7 | bool |
| 8 | help |
| 9 | Choose this option if you have PCH-M chipset. |
| 10 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 11 | if SOC_INTEL_ALDERLAKE |
| 12 | |
| 13 | config CPU_SPECIFIC_OPTIONS |
| 14 | def_bool y |
Angel Pons | a25eaff | 2020-09-23 15:37:15 +0200 | [diff] [blame] | 15 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 16 | select ARCH_ALL_STAGES_X86_32 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 17 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 18 | select CACHE_MRC_SETTINGS |
| 19 | select CPU_INTEL_COMMON |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 20 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 21 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Eric Lai | 4ea47c3 | 2020-12-21 16:57:49 +0800 | [diff] [blame] | 22 | select DRIVERS_USB_ACPI |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 23 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 24 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 25 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 26 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 27 | select GENERIC_GPIO_LIB |
| 28 | select HAVE_FSP_GOP |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 29 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 30 | select HAVE_SMI_HANDLER |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 31 | select IDT_IN_EVERY_STAGE |
| 32 | select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 33 | select INTEL_GMA_ACPI |
| 34 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 35 | select IOAPIC |
Subrata Banik | 0aed4e5 | 2020-10-12 17:27:31 +0530 | [diff] [blame] | 36 | select INTEL_TME |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 37 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 38 | select PARALLEL_MP |
| 39 | select PARALLEL_MP_AP_WORK |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 40 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 41 | select PLATFORM_USES_FSP2_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 42 | select FSP_PEIM_TO_PEIM_INTERFACE |
| 43 | select REG_SCRIPT |
| 44 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
| 45 | select PMC_LOW_POWER_MODE_PROGRAM |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 46 | select SOC_INTEL_COMMON |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_CPU |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 54 | select SOC_INTEL_COMMON_BLOCK_DTT |
| 55 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_SA |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 60 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Eric Lai | 4ea47c3 | 2020-12-21 16:57:49 +0800 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 62 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
| 63 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_FSP_RESET |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_PCH_BASE |
| 66 | select SOC_INTEL_COMMON_RESET |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 67 | select SSE2 |
| 68 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 69 | select TSC_MONOTONIC_TIMER |
| 70 | select UDELAY_TSC |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 71 | select UDK_202005_BINDING |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 72 | select DISPLAY_FSP_VERSION_INFO |
| 73 | select HECI_DISABLE_USING_SMM |
| 74 | |
| 75 | config MAX_CPUS |
| 76 | int |
| 77 | default 24 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 78 | |
| 79 | config DCACHE_RAM_BASE |
| 80 | default 0xfef00000 |
| 81 | |
| 82 | config DCACHE_RAM_SIZE |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 83 | default 0xc0000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 84 | help |
| 85 | The size of the cache-as-ram region required during bootblock |
| 86 | and/or romstage. |
| 87 | |
| 88 | config DCACHE_BSP_STACK_SIZE |
| 89 | hex |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 90 | default 0x80400 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 91 | help |
| 92 | The amount of anticipated stack usage in CAR by bootblock and |
| 93 | other stages. In the case of FSP_USES_CB_STACK default value will be |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 94 | sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 95 | (~1KiB). |
| 96 | |
| 97 | config FSP_TEMP_RAM_SIZE |
| 98 | hex |
| 99 | default 0x20000 |
| 100 | help |
| 101 | The amount of anticipated heap usage in CAR by FSP. |
| 102 | Refer to Platform FSP integration guide document to know |
| 103 | the exact FSP requirement for Heap setup. |
| 104 | |
Tim Wawrzynczak | 092813a | 2020-11-24 13:48:56 -0700 | [diff] [blame] | 105 | config CHIPSET_DEVICETREE |
| 106 | string |
| 107 | default "soc/intel/alderlake/chipset.cb" |
| 108 | |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 109 | config EXT_BIOS_WIN_BASE |
| 110 | default 0xf8000000 |
| 111 | |
| 112 | config EXT_BIOS_WIN_SIZE |
| 113 | default 0x2000000 |
| 114 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 115 | config IFD_CHIPSET |
| 116 | string |
| 117 | default "adl" |
| 118 | |
| 119 | config IED_REGION_SIZE |
| 120 | hex |
| 121 | default 0x400000 |
| 122 | |
| 123 | config HEAP_SIZE |
| 124 | hex |
| 125 | default 0x10000 |
| 126 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 127 | config MAX_PCH_ROOT_PORTS |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 128 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 129 | default 10 if SOC_INTEL_ALDERLAKE_PCH_M |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 130 | default 12 |
| 131 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 132 | config MAX_CPU_ROOT_PORTS |
| 133 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 134 | default 1 if SOC_INTEL_ALDERLAKE_PCH_M |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 135 | default 3 |
| 136 | |
| 137 | config MAX_ROOT_PORTS |
| 138 | int |
| 139 | default MAX_PCH_ROOT_PORTS |
| 140 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 141 | config MAX_PCIE_CLOCKS |
| 142 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 143 | default 10 if SOC_INTEL_ALDERLAKE_PCH_M |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 144 | default 12 |
| 145 | |
| 146 | config SMM_TSEG_SIZE |
| 147 | hex |
| 148 | default 0x800000 |
| 149 | |
| 150 | config SMM_RESERVED_SIZE |
| 151 | hex |
| 152 | default 0x200000 |
| 153 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 154 | config PCR_BASE_ADDRESS |
| 155 | hex |
| 156 | default 0xfd000000 |
| 157 | help |
| 158 | This option allows you to select MMIO Base Address of sideband bus. |
| 159 | |
| 160 | config MMCONF_BASE_ADDRESS |
| 161 | hex |
| 162 | default 0xc0000000 |
| 163 | |
| 164 | config CPU_BCLK_MHZ |
| 165 | int |
| 166 | default 100 |
| 167 | |
| 168 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 169 | int |
| 170 | default 120 |
| 171 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 172 | config CPU_XTAL_HZ |
| 173 | default 38400000 |
| 174 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 175 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 176 | int |
| 177 | default 133 |
| 178 | |
| 179 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 180 | int |
| 181 | default 7 |
| 182 | |
| 183 | config SOC_INTEL_I2C_DEV_MAX |
| 184 | int |
| 185 | default 6 |
| 186 | |
| 187 | config SOC_INTEL_UART_DEV_MAX |
| 188 | int |
| 189 | default 7 |
| 190 | |
| 191 | config CONSOLE_UART_BASE_ADDRESS |
| 192 | hex |
Bora Guvendik | 2a70419 | 2020-11-16 11:23:48 -0800 | [diff] [blame] | 193 | default 0xfe03e000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 194 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 195 | |
| 196 | # Clock divider parameters for 115200 baud rate |
| 197 | # Baudrate = (UART source clcok * M) /(N *16) |
| 198 | # ADL UART source clock: 120MHz |
| 199 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 200 | hex |
| 201 | default 0x25a |
| 202 | |
| 203 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 204 | hex |
| 205 | default 0x7fff |
| 206 | |
| 207 | config CHROMEOS |
| 208 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 209 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 210 | config VBOOT |
| 211 | select VBOOT_SEPARATE_VERSTAGE |
| 212 | select VBOOT_MUST_REQUEST_DISPLAY |
| 213 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 214 | select VBOOT_VBNV_CMOS |
| 215 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 216 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 217 | config C_ENV_BOOTBLOCK_SIZE |
| 218 | hex |
| 219 | default 0xC000 |
| 220 | |
| 221 | config CBFS_SIZE |
| 222 | hex |
| 223 | default 0x200000 |
| 224 | |
| 225 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 226 | hex |
| 227 | default 0x1400 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 228 | |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 229 | config FSP_HEADER_PATH |
| 230 | string "Location of FSP headers" |
| 231 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" |
| 232 | |
| 233 | config FSP_FD_PATH |
| 234 | string |
| 235 | depends on FSP_USE_REPO |
| 236 | default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 237 | |
| 238 | config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT |
| 239 | int "Debug Consent for ADL" |
| 240 | # USB DBC is more common for developers so make this default to 3 if |
| 241 | # SOC_INTEL_DEBUG_CONSENT=y |
| 242 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 243 | default 0 |
| 244 | help |
| 245 | This is to control debug interface on SOC. |
| 246 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 247 | PlatformDebugConsent in FspmUpd.h has the details. |
| 248 | |
| 249 | Desired platform debug type are |
| 250 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 251 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 252 | 6:Enable (2-wire DCI OOB), 7:Manual |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 253 | endif |