Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
Duncan Laurie | 0d0b3c5 | 2014-02-10 11:34:27 -0800 | [diff] [blame] | 22 | #include <bootstate.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <console/console.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <cpu/cpu.h> |
| 28 | #include <cpu/x86/cache.h> |
| 29 | #include <cpu/x86/smm.h> |
| 30 | #include <string.h> |
| 31 | #include "pch.h" |
| 32 | |
Aaron Durbin | af3158c | 2013-03-27 20:57:28 -0500 | [diff] [blame] | 33 | void southbridge_smm_clear_state(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | { |
| 35 | u32 smi_en; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 37 | #if CONFIG_ELOG |
| 38 | /* Log events from chipset before clearing */ |
| 39 | pch_log_state(); |
| 40 | #endif |
| 41 | printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 42 | printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase()); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 44 | smi_en = inl(get_pmbase() + SMI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 45 | if (smi_en & APMC_EN) { |
| 46 | printk(BIOS_INFO, "SMI# handler already enabled?\n"); |
| 47 | return; |
| 48 | } |
| 49 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 50 | printk(BIOS_DEBUG, "\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 51 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 52 | /* Dump and clear status registers */ |
| 53 | clear_smi_status(); |
| 54 | clear_pm1_status(); |
| 55 | clear_tco_status(); |
| 56 | clear_gpe_status(); |
Aaron Durbin | af3158c | 2013-03-27 20:57:28 -0500 | [diff] [blame] | 57 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | |
Aaron Durbin | af3158c | 2013-03-27 20:57:28 -0500 | [diff] [blame] | 59 | void southbridge_smm_enable_smi(void) |
| 60 | { |
| 61 | printk(BIOS_DEBUG, "Enabling SMIs.\n"); |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 62 | /* Configure events */ |
| 63 | enable_pm1(PWRBTN_EN | GBL_EN); |
| 64 | disable_gpe(PME_B0_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 65 | |
| 66 | /* Enable SMI generation: |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 67 | * - on APMC writes (io 0xb2) |
| 68 | * - on writes to SLP_EN (sleep states) |
| 69 | * - on writes to GBL_RLS (bios commands) |
| 70 | * No SMIs: |
| 71 | * - on microcontroller writes (io 0x62/0x66) |
Duncan Laurie | d5acaaf | 2013-12-17 15:35:51 -0800 | [diff] [blame] | 72 | * - on TCO events |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 73 | */ |
Duncan Laurie | d5acaaf | 2013-12-17 15:35:51 -0800 | [diff] [blame] | 74 | enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 75 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 76 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 77 | void southbridge_trigger_smi(void) |
| 78 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 79 | /** |
| 80 | * There are several methods of raising a controlled SMI# via |
| 81 | * software, among them: |
| 82 | * - Writes to io 0xb2 (APMC) |
| 83 | * - Writes to the Local Apic ICR with Delivery mode SMI. |
| 84 | * |
| 85 | * Using the local apic is a bit more tricky. According to |
| 86 | * AMD Family 11 Processor BKDG no destination shorthand must be |
| 87 | * used. |
| 88 | * The whole SMM initialization is quite a bit hardware specific, so |
| 89 | * I'm not too worried about the better of the methods at the moment |
| 90 | */ |
| 91 | |
| 92 | /* raise an SMI interrupt */ |
| 93 | printk(BIOS_SPEW, " ... raise SMI#\n"); |
| 94 | outb(0x00, 0xb2); |
| 95 | } |
| 96 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 97 | void southbridge_clear_smi_status(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 98 | { |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 99 | /* Clear SMI status */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 100 | clear_smi_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 101 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 102 | /* Clear PM1 status */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 103 | clear_pm1_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 104 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 105 | /* Set EOS bit so other SMIs can occur. */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 106 | enable_smi(EOS); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 107 | } |
| 108 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 109 | void smm_setup_structures(void *gnvs, void *tcg, void *smi1) |
| 110 | { |
| 111 | /* |
| 112 | * Issue SMI to set the gnvs pointer in SMM. |
| 113 | * tcg and smi1 are unused. |
| 114 | * |
| 115 | * EAX = APM_CNT_GNVS_UPDATE |
| 116 | * EBX = gnvs pointer |
| 117 | * EDX = APM_CNT |
| 118 | */ |
| 119 | asm volatile ( |
| 120 | "outb %%al, %%dx\n\t" |
| 121 | : /* ignore result */ |
| 122 | : "a" (APM_CNT_GNVS_UPDATE), |
| 123 | "b" ((u32)gnvs), |
| 124 | "d" (APM_CNT) |
| 125 | ); |
| 126 | } |
Duncan Laurie | 0d0b3c5 | 2014-02-10 11:34:27 -0800 | [diff] [blame] | 127 | |
| 128 | /* |
| 129 | * Finalize system before payload boot if not in ChromeOS environment. |
| 130 | */ |
| 131 | #if !CONFIG_CHROMEOS |
| 132 | |
| 133 | static void finalize_boot(void *unused) |
| 134 | { |
| 135 | outb(0xcb, 0xb2); |
| 136 | } |
| 137 | |
Aaron Durbin | 9ef9d85 | 2015-03-16 17:30:09 -0500 | [diff] [blame^] | 138 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); |
Duncan Laurie | 0d0b3c5 | 2014-02-10 11:34:27 -0800 | [diff] [blame] | 139 | |
| 140 | #endif |