Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stddef.h> |
| 17 | #include <arch/cpu.h> |
| 18 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 19 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 21 | #include <bootblock_common.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <cbmem.h> |
| 24 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | 7cdb047 | 2019-08-08 11:16:06 +0300 | [diff] [blame] | 25 | #include <cpu/x86/smm.h> |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 26 | #if CONFIG(EC_GOOGLE_CHROMEEC) |
Aaron Durbin | 3e0eea1 | 2013-10-28 11:20:35 -0500 | [diff] [blame] | 27 | #include <ec/google/chromeec/ec.h> |
| 28 | #endif |
Aaron Durbin | a8e9b63 | 2013-10-30 15:46:07 -0500 | [diff] [blame] | 29 | #include <elog.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 30 | #include <program_loading.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 31 | #include <romstage_handoff.h> |
Aaron Durbin | bd74a4b | 2015-03-06 23:17:33 -0600 | [diff] [blame] | 32 | #include <stage_cache.h> |
Aaron Durbin | afe8aee | 2016-11-29 21:37:42 -0600 | [diff] [blame] | 33 | #include <string.h> |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 34 | #include <timestamp.h> |
Aaron Durbin | ebf7ec5 | 2013-11-14 13:47:08 -0600 | [diff] [blame] | 35 | #include <vendorcode/google/chromeos/chromeos.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 36 | #include <soc/gpio.h> |
| 37 | #include <soc/iomap.h> |
| 38 | #include <soc/lpc.h> |
Kyösti Mälkki | 8e23bac | 2019-08-17 06:47:50 +0300 | [diff] [blame] | 39 | #include <soc/msr.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 40 | #include <soc/pci_devs.h> |
| 41 | #include <soc/pmc.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 42 | #include <soc/romstage.h> |
| 43 | #include <soc/smm.h> |
| 44 | #include <soc/spi.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 45 | |
| 46 | /* The cache-as-ram assembly file calls romstage_main() after setting up |
| 47 | * cache-as-ram. romstage_main() will then call the mainboards's |
| 48 | * mainboard_romstage_entry() function. That function then calls |
| 49 | * romstage_common() below. The reason for the back and forth is to provide |
| 50 | * common entry point from cache-as-ram while still allowing for code sharing. |
| 51 | * Because we can't use global variables the stack is used for allocations -- |
| 52 | * thus the need to call back and forth. */ |
| 53 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 54 | static struct postcar_frame early_mtrrs; |
| 55 | |
| 56 | static void fill_postcar_frame(struct postcar_frame *pcf); |
| 57 | |
| 58 | /* prepare_and_run_postcar() determines the stack to use after |
| 59 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
| 60 | static void prepare_and_run_postcar(struct postcar_frame *pcf) |
| 61 | { |
| 62 | if (postcar_frame_init(pcf, 0)) |
| 63 | die("Unable to initialize postcar frame.\n"); |
| 64 | |
| 65 | fill_postcar_frame(pcf); |
| 66 | |
Kyösti Mälkki | 544878b | 2019-08-09 11:41:15 +0300 | [diff] [blame] | 67 | postcar_frame_common_mtrrs(pcf); |
| 68 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 69 | run_postcar_phase(pcf); |
| 70 | /* We do not return here. */ |
| 71 | } |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 72 | |
| 73 | static void program_base_addresses(void) |
| 74 | { |
| 75 | uint32_t reg; |
| 76 | const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); |
| 77 | |
| 78 | /* Memory Mapped IO registers. */ |
| 79 | reg = PMC_BASE_ADDRESS | 2; |
| 80 | pci_write_config32(lpc_dev, PBASE, reg); |
| 81 | reg = IO_BASE_ADDRESS | 2; |
| 82 | pci_write_config32(lpc_dev, IOBASE, reg); |
| 83 | reg = ILB_BASE_ADDRESS | 2; |
| 84 | pci_write_config32(lpc_dev, IBASE, reg); |
| 85 | reg = SPI_BASE_ADDRESS | 2; |
| 86 | pci_write_config32(lpc_dev, SBASE, reg); |
| 87 | reg = MPHY_BASE_ADDRESS | 2; |
| 88 | pci_write_config32(lpc_dev, MPBASE, reg); |
Aaron Durbin | a64ef62 | 2013-10-03 12:56:37 -0500 | [diff] [blame] | 89 | reg = PUNIT_BASE_ADDRESS | 2; |
| 90 | pci_write_config32(lpc_dev, PUBASE, reg); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 91 | reg = RCBA_BASE_ADDRESS | 1; |
| 92 | pci_write_config32(lpc_dev, RCBA, reg); |
| 93 | |
| 94 | /* IO Port Registers. */ |
| 95 | reg = ACPI_BASE_ADDRESS | 2; |
| 96 | pci_write_config32(lpc_dev, ABASE, reg); |
| 97 | reg = GPIO_BASE_ADDRESS | 2; |
| 98 | pci_write_config32(lpc_dev, GBASE, reg); |
| 99 | } |
| 100 | |
Aaron Durbin | 6f9947a | 2013-11-18 11:16:20 -0600 | [diff] [blame] | 101 | static void spi_init(void) |
| 102 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 103 | u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); |
| 104 | u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 105 | uint32_t reg; |
| 106 | |
| 107 | /* Disable generating SMI when setting WPD bit. */ |
| 108 | write32(scs, read32(scs) & ~SMIWPEN); |
| 109 | /* |
| 110 | * Enable caching and prefetching in the SPI controller. Disable |
| 111 | * the SMM-only BIOS write and set WPD bit. |
| 112 | */ |
| 113 | reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; |
| 114 | reg &= ~EISS; |
| 115 | write32(bcr, reg); |
Aaron Durbin | 6f9947a | 2013-11-18 11:16:20 -0600 | [diff] [blame] | 116 | } |
| 117 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 118 | /* Entry from cache-as-ram.inc. */ |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 119 | static void romstage_main(uint64_t tsc) |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 120 | { |
| 121 | struct romstage_params rp = { |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 122 | .mrc_params = NULL, |
| 123 | }; |
| 124 | |
| 125 | /* Save initial timestamp from bootblock. */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 126 | timestamp_init(tsc); |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 127 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 128 | /* Save romstage begin */ |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 129 | timestamp_add_now(TS_START_ROMSTAGE); |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 130 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 131 | program_base_addresses(); |
| 132 | |
Aaron Durbin | fd039f7 | 2013-10-04 11:11:52 -0500 | [diff] [blame] | 133 | tco_disable(); |
| 134 | |
Kyösti Mälkki | 8e23bac | 2019-08-17 06:47:50 +0300 | [diff] [blame] | 135 | if (CONFIG(ENABLE_BUILTIN_COM1)) |
| 136 | byt_config_com1_and_enable(); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 137 | |
| 138 | console_init(); |
| 139 | |
Aaron Durbin | 6f9947a | 2013-11-18 11:16:20 -0600 | [diff] [blame] | 140 | spi_init(); |
| 141 | |
Aaron Durbin | bb3ee83 | 2013-10-07 17:12:20 -0500 | [diff] [blame] | 142 | set_max_freq(); |
| 143 | |
Aaron Durbin | 189aa3e | 2013-10-04 11:17:45 -0500 | [diff] [blame] | 144 | punit_init(); |
| 145 | |
Aaron Durbin | ecf9086 | 2013-09-24 12:36:14 -0500 | [diff] [blame] | 146 | gfx_init(); |
| 147 | |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 148 | /* Call into mainboard. */ |
Kyösti Mälkki | c274185 | 2019-08-16 15:13:00 +0300 | [diff] [blame] | 149 | mainboard_romstage_entry_rp(&rp); |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 150 | |
Kyösti Mälkki | 7cdb047 | 2019-08-08 11:16:06 +0300 | [diff] [blame] | 151 | if (CONFIG(SMM_TSEG)) |
| 152 | smm_list_regions(); |
| 153 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 154 | prepare_and_run_postcar(&early_mtrrs); |
| 155 | /* We do not return here. */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 156 | } |
| 157 | |
| 158 | /* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, |
| 159 | * keeping changes in cache_as_ram.S easy to manage. |
| 160 | */ |
| 161 | asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) |
| 162 | { |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 163 | romstage_main(base_timestamp); |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 164 | } |
| 165 | |
Arthur Heymans | e228678 | 2018-12-29 14:01:12 +0100 | [diff] [blame] | 166 | static struct chipset_power_state power_state; |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 167 | |
Aaron Durbin | 41607a4 | 2015-06-09 13:54:10 -0500 | [diff] [blame] | 168 | static void migrate_power_state(int is_recovery) |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 169 | { |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 170 | struct chipset_power_state *ps_cbmem; |
| 171 | struct chipset_power_state *ps_car; |
| 172 | |
Arthur Heymans | e228678 | 2018-12-29 14:01:12 +0100 | [diff] [blame] | 173 | ps_car = &power_state; |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 174 | ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); |
| 175 | |
| 176 | if (ps_cbmem == NULL) { |
| 177 | printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); |
| 178 | return; |
| 179 | } |
| 180 | memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); |
| 181 | } |
Kyösti Mälkki | 4fbac46 | 2015-01-07 04:48:43 +0200 | [diff] [blame] | 182 | ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 183 | |
| 184 | static struct chipset_power_state *fill_power_state(void) |
| 185 | { |
Arthur Heymans | e228678 | 2018-12-29 14:01:12 +0100 | [diff] [blame] | 186 | struct chipset_power_state *ps = &power_state; |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 187 | |
| 188 | ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 189 | ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); |
| 190 | ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 191 | ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); |
| 192 | ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); |
| 193 | ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 194 | ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); |
| 195 | ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); |
| 196 | ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2)); |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 197 | |
| 198 | printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 199 | ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); |
| 200 | printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", |
| 201 | ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); |
| 202 | printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", |
| 203 | ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); |
| 204 | |
| 205 | return ps; |
| 206 | } |
| 207 | |
| 208 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 209 | static int chipset_prev_sleep_state(struct chipset_power_state *ps) |
| 210 | { |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 211 | /* Default to S0. */ |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 212 | int prev_sleep_state = ACPI_S0; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 213 | |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 214 | if (ps->pm1_sts & WAK_STS) { |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 215 | switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { |
| 216 | case ACPI_S3: |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 217 | if (CONFIG(HAVE_ACPI_RESUME)) |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 218 | prev_sleep_state = ACPI_S3; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 219 | break; |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 220 | case ACPI_S5: |
| 221 | prev_sleep_state = ACPI_S5; |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 222 | break; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 223 | } |
| 224 | /* Clear SLP_TYP. */ |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 225 | outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 226 | } |
| 227 | |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 228 | if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 229 | prev_sleep_state = ACPI_S5; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 230 | } |
| 231 | |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 232 | return prev_sleep_state; |
| 233 | } |
| 234 | |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 235 | /* Entry from the mainboard. */ |
| 236 | void romstage_common(struct romstage_params *params) |
| 237 | { |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 238 | struct chipset_power_state *ps; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 239 | int prev_sleep_state; |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 240 | |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 241 | timestamp_add_now(TS_BEFORE_INITRAM); |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 242 | |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 243 | ps = fill_power_state(); |
| 244 | prev_sleep_state = chipset_prev_sleep_state(ps); |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 245 | |
| 246 | printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); |
| 247 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 248 | #if CONFIG(ELOG_BOOT_COUNT) |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 249 | if (prev_sleep_state != ACPI_S3) |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 250 | boot_count_increment(); |
| 251 | #endif |
| 252 | |
| 253 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 254 | /* Initialize RAM */ |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 255 | raminit(params->mrc_params, prev_sleep_state); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 256 | |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 257 | timestamp_add_now(TS_AFTER_INITRAM); |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 258 | |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 259 | romstage_handoff_init(prev_sleep_state == ACPI_S3); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 260 | } |
| 261 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 262 | static void fill_postcar_frame(struct postcar_frame *pcf) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 263 | { |
Arthur Heymans | f6cfbf3 | 2018-11-29 14:08:15 +0100 | [diff] [blame] | 264 | uintptr_t top_of_ram; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 265 | |
Arthur Heymans | f6cfbf3 | 2018-11-29 14:08:15 +0100 | [diff] [blame] | 266 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 267 | * above top of the ram. This satisfies MTRR alignment requirement |
| 268 | * with different TSEG size configurations. |
| 269 | */ |
| 270 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 271 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, |
Arthur Heymans | f6cfbf3 | 2018-11-29 14:08:15 +0100 | [diff] [blame] | 272 | MTRR_TYPE_WRBACK); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 273 | } |