Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Subrata Banik | a4b11e5c | 2017-02-03 18:57:49 +0530 | [diff] [blame] | 4 | * Copyright (C) 2016-2017 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 16 | #include <chip.h> |
Duncan Laurie | 7d48410 | 2017-01-09 22:23:39 -0800 | [diff] [blame] | 17 | #include <bootmode.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 18 | #include <bootstate.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <fsp/api.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 21 | #include <arch/acpi.h> |
| 22 | #include <chip.h> |
| 23 | #include <bootstate.h> |
| 24 | #include <console/console.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <fsp/api.h> |
| 28 | #include <fsp/util.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 29 | #include <romstage_handoff.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 30 | #include <soc/acpi.h> |
Patrick Georgi | c6a0050 | 2017-10-05 18:19:29 +0200 | [diff] [blame] | 31 | #include <soc/intel/common/vbt.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 32 | #include <soc/interrupt.h> |
| 33 | #include <soc/irq.h> |
| 34 | #include <soc/pci_devs.h> |
| 35 | #include <soc/ramstage.h> |
| 36 | #include <string.h> |
| 37 | |
| 38 | void soc_init_pre_device(void *chip_info) |
| 39 | { |
| 40 | /* Perform silicon specific init. */ |
Aaron Durbin | 6c191d8 | 2016-11-29 21:22:42 -0600 | [diff] [blame] | 41 | fsp_silicon_init(romstage_handoff_is_resume()); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 42 | } |
| 43 | |
Furquan Shaikh | c248044 | 2017-02-20 13:41:56 -0800 | [diff] [blame] | 44 | void soc_fsp_load(void) |
| 45 | { |
| 46 | fsps_load(romstage_handoff_is_resume()); |
| 47 | } |
| 48 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 49 | static void pci_domain_set_resources(device_t dev) |
| 50 | { |
| 51 | assign_resources(dev->link_list); |
| 52 | } |
| 53 | |
| 54 | static struct device_operations pci_domain_ops = { |
| 55 | .read_resources = &pci_domain_read_resources, |
| 56 | .set_resources = &pci_domain_set_resources, |
| 57 | .scan_bus = &pci_domain_scan_bus, |
| 58 | .ops_pci_bus = &pci_bus_default_ops, |
| 59 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
| 60 | .acpi_name = &soc_acpi_name, |
| 61 | #endif |
| 62 | }; |
| 63 | |
| 64 | static struct device_operations cpu_bus_ops = { |
| 65 | .read_resources = DEVICE_NOOP, |
| 66 | .set_resources = DEVICE_NOOP, |
| 67 | .enable_resources = DEVICE_NOOP, |
Subrata Banik | a4b11e5c | 2017-02-03 18:57:49 +0530 | [diff] [blame] | 68 | .init = DEVICE_NOOP, |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 69 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
| 70 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
| 71 | #endif |
| 72 | }; |
| 73 | |
| 74 | static void soc_enable(device_t dev) |
| 75 | { |
| 76 | /* Set the operations if it is a special bus type */ |
| 77 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 78 | dev->ops = &pci_domain_ops; |
| 79 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 80 | dev->ops = &cpu_bus_ops; |
| 81 | } else if (dev->path.type == DEVICE_PATH_PCI) { |
| 82 | /* Handle PCH device enable */ |
| 83 | if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD && |
| 84 | (dev->ops == NULL || dev->ops->enable == NULL)) { |
| 85 | pch_enable_dev(dev); |
| 86 | } |
| 87 | } |
| 88 | } |
| 89 | |
| 90 | struct chip_operations soc_intel_skylake_ops = { |
| 91 | CHIP_NAME("Intel 6th Gen") |
| 92 | .enable_dev = &soc_enable, |
| 93 | .init = &soc_init_pre_device, |
| 94 | }; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 95 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 96 | /* UPD parameters to be initialized before SiliconInit */ |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 97 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 98 | { |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 99 | FSP_S_CONFIG *params = &supd->FspsConfig; |
| 100 | FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; |
| 101 | static struct soc_intel_skylake_config *config; |
| 102 | uintptr_t vbt_data = 0; |
| 103 | |
| 104 | int i; |
| 105 | |
| 106 | int is_s3_wakeup = acpi_is_wakeup_s3(); |
| 107 | |
| 108 | struct device *dev = SA_DEV_ROOT; |
| 109 | if (!dev || !dev->chip_info) { |
| 110 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 111 | return; |
| 112 | } |
| 113 | config = dev->chip_info; |
| 114 | |
| 115 | mainboard_silicon_init_params(params); |
| 116 | |
| 117 | /* Load VBT */ |
Duncan Laurie | 7d48410 | 2017-01-09 22:23:39 -0800 | [diff] [blame] | 118 | if (is_s3_wakeup) { |
| 119 | printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n"); |
Patrick Georgi | c6a0050 | 2017-10-05 18:19:29 +0200 | [diff] [blame] | 120 | } else if (display_init_required() && IS_ENABLED(CONFIG_RUN_FSP_GOP)) { |
Duncan Laurie | 7d48410 | 2017-01-09 22:23:39 -0800 | [diff] [blame] | 121 | /* Get VBT data */ |
Patrick Georgi | c6a0050 | 2017-10-05 18:19:29 +0200 | [diff] [blame] | 122 | vbt_data = (uintptr_t)locate_vbt(); |
Duncan Laurie | 7d48410 | 2017-01-09 22:23:39 -0800 | [diff] [blame] | 123 | if (vbt_data) |
| 124 | printk(BIOS_DEBUG, "Passing VBT to GOP\n"); |
| 125 | else |
| 126 | printk(BIOS_DEBUG, "VBT not found!\n"); |
| 127 | } else { |
| 128 | printk(BIOS_DEBUG, "Not passing VBT to GOP\n"); |
| 129 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 130 | params->GraphicsConfigPtr = (u32) vbt_data; |
| 131 | |
| 132 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 133 | params->PortUsb20Enable[i] = |
| 134 | config->usb2_ports[i].enable; |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 135 | params->Usb2OverCurrentPin[i] = |
| 136 | config->usb2_ports[i].ocpin; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 137 | params->Usb2AfePetxiset[i] = |
| 138 | config->usb2_ports[i].pre_emp_bias; |
| 139 | params->Usb2AfeTxiset[i] = |
| 140 | config->usb2_ports[i].tx_bias; |
| 141 | params->Usb2AfePredeemp[i] = |
| 142 | config->usb2_ports[i].tx_emp_enable; |
| 143 | params->Usb2AfePehalfbit[i] = |
| 144 | config->usb2_ports[i].pre_emp_bit; |
| 145 | } |
| 146 | |
| 147 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 148 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 149 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 150 | if (config->usb3_ports[i].tx_de_emp) { |
| 151 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 152 | params->Usb3HsioTxDeEmph[i] = |
| 153 | config->usb3_ports[i].tx_de_emp; |
| 154 | } |
| 155 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 156 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 157 | params->Usb3HsioTxDownscaleAmp[i] = |
| 158 | config->usb3_ports[i].tx_downscale_amp; |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 163 | sizeof(params->SataPortsEnable)); |
| 164 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 165 | sizeof(params->SataPortsDevSlp)); |
| 166 | memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, |
| 167 | sizeof(params->PcieRpClkReqSupport)); |
| 168 | memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, |
| 169 | sizeof(params->PcieRpClkReqNumber)); |
Rizwan Qureshi | 6ab4ed4 | 2017-09-05 14:18:25 +0530 | [diff] [blame] | 170 | memcpy(params->PcieRpAdvancedErrorReporting, |
| 171 | config->PcieRpAdvancedErrorReporting, |
| 172 | sizeof(params->PcieRpAdvancedErrorReporting)); |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 173 | memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, |
| 174 | sizeof(params->PcieRpLtrEnable)); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 175 | |
Naresh G Solanki | eedf6d8 | 2016-11-16 21:27:38 +0530 | [diff] [blame] | 176 | /* disable Legacy PME */ |
| 177 | memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); |
| 178 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 179 | memcpy(params->SerialIoDevMode, config->SerialIoDevMode, |
| 180 | sizeof(params->SerialIoDevMode)); |
| 181 | |
| 182 | params->PchCio2Enable = config->Cio2Enable; |
Rizwan Qureshi | c2c8a74 | 2017-01-13 22:04:11 +0530 | [diff] [blame] | 183 | params->SaImguEnable = config->SaImguEnable; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 184 | params->Heci3Enabled = config->Heci3Enabled; |
| 185 | |
| 186 | params->LogoPtr = config->LogoPtr; |
| 187 | params->LogoSize = config->LogoSize; |
| 188 | |
| 189 | params->CpuConfig.Bits.VmxEnable = config->VmxEnable; |
| 190 | |
| 191 | params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; |
| 192 | params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; |
| 193 | params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; |
| 194 | |
| 195 | params->PchLanEnable = config->EnableLan; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 196 | params->SataSalpSupport = config->SataSalpSupport; |
| 197 | params->SsicPortEnable = config->SsicPortEnable; |
| 198 | params->ScsEmmcEnabled = config->ScsEmmcEnabled; |
| 199 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
| 200 | params->ScsSdCardEnabled = config->ScsSdCardEnabled; |
| 201 | params->PchIshEnable = config->IshEnable; |
| 202 | params->PchHdaEnable = config->EnableAzalia; |
| 203 | params->PchHdaIoBufferOwnership = config->IoBufferOwnership; |
| 204 | params->PchHdaDspEnable = config->DspEnable; |
| 205 | params->XdciEnable = config->XdciEnable; |
| 206 | params->Device4Enable = config->Device4Enable; |
| 207 | params->SataEnable = config->EnableSata; |
| 208 | params->SataMode = config->SataMode; |
| 209 | tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 210 | tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; |
Barnali Sarkar | fbf1018 | 2017-08-11 18:38:38 +0530 | [diff] [blame] | 211 | /* |
| 212 | * To disable HECI, the Psf needs to be left unlocked |
| 213 | * by FSP till end of post sequence. Based on the devicetree |
| 214 | * setting, we set the appropriate PsfUnlock policy in FSP, |
| 215 | * do the changes and then lock it back in coreboot during finalize. |
| 216 | */ |
| 217 | tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 218 | if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { |
| 219 | tconfig->PchLockDownBiosInterface = 0; |
| 220 | params->PchLockDownBiosLock = 0; |
| 221 | params->PchLockDownSpiEiss = 0; |
| 222 | /* |
| 223 | * Skip Spi Flash Lockdown from inside FSP. |
| 224 | * Making this config "0" means FSP won't set the FLOCKDN bit |
| 225 | * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). |
| 226 | * So, it becomes coreboot's responsibility to set this bit |
| 227 | * before end of POST for security concerns. |
| 228 | */ |
| 229 | params->SpiFlashCfgLockDown = 0; |
| 230 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 231 | params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; |
| 232 | params->PchSubSystemId = config->PchConfigSubSystemId; |
| 233 | params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; |
| 234 | params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; |
| 235 | params->PchPmDeepSxPol = config->PmConfigDeepSxPol; |
Duncan Laurie | 25c7d93 | 2017-02-17 17:16:43 -0800 | [diff] [blame] | 236 | params->PchPmSlpS0Enable = config->s0ix_enable; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 237 | params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; |
| 238 | params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; |
| 239 | params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; |
| 240 | params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; |
| 241 | params->PchPmLpcClockRun = config->PmConfigPciClockRun; |
| 242 | params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; |
| 243 | params->PchPmPwrBtnOverridePeriod = |
| 244 | config->PmConfigPwrBtnOverridePeriod; |
| 245 | params->PchPmPwrCycDur = config->PmConfigPwrCycDur; |
Rizwan Qureshi | 0da186c | 2017-02-23 14:43:39 +0530 | [diff] [blame] | 246 | |
| 247 | /* Indicate whether platform supports Voltage Margining */ |
| 248 | params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable; |
| 249 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 250 | params->PchSirqEnable = config->SerialIrqConfigSirqEnable; |
| 251 | params->PchSirqMode = config->SerialIrqConfigSirqMode; |
| 252 | |
| 253 | params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit; |
| 254 | |
| 255 | for (i = 0; i < ARRAY_SIZE(config->i2c); i++) |
Aaron Durbin | ed14a4e | 2016-11-09 17:04:15 -0600 | [diff] [blame] | 256 | params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 257 | |
| 258 | for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 259 | fill_vr_domain_config(params, i, &config->domain_vr_config[i]); |
| 260 | |
| 261 | /* Show SPI controller if enabled in devicetree.cb */ |
| 262 | dev = dev_find_slot(0, PCH_DEVFN_SPI); |
| 263 | params->ShowSpiController = dev->enabled; |
| 264 | |
Rizwan Qureshi | 6467014 | 2016-11-23 15:25:19 +0530 | [diff] [blame] | 265 | /* |
| 266 | * Send VR specific mailbox commands: |
| 267 | * 000b - no VR specific command sent |
| 268 | * 001b - VR mailbox command specifically for the MPS IMPV8 VR |
Lee Leahy | f4c4ab9 | 2017-03-16 17:08:03 -0700 | [diff] [blame] | 269 | * will be sent |
Rizwan Qureshi | 6467014 | 2016-11-23 15:25:19 +0530 | [diff] [blame] | 270 | * 010b - VR specific command sent for PS4 exit issue |
| 271 | * 100b - VR specific command sent for MPS VR decay issue |
| 272 | */ |
| 273 | params->SendVrMbxCmd1 = config->SendVrMbxCmd; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 274 | |
Rizwan Qureshi | b3e18c7 | 2017-09-25 17:35:15 +0530 | [diff] [blame] | 275 | /* |
| 276 | * Activates VR mailbox command for Intersil VR C-state issues. |
| 277 | * 0 - no mailbox command sent. |
| 278 | * 1 - VR mailbox command sent for IA/GT rails only. |
| 279 | * 2 - VR mailbox command sent for IA/GT/SA rails. |
| 280 | */ |
| 281 | params->IslVrCmd = config->IslVrCmd; |
| 282 | |
Duncan Laurie | b2aac85 | 2017-03-07 19:12:02 -0800 | [diff] [blame] | 283 | /* Acoustic Noise Mitigation */ |
| 284 | params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; |
| 285 | params->SlowSlewRateForIa = config->SlowSlewRateForIa; |
| 286 | params->SlowSlewRateForGt = config->SlowSlewRateForGt; |
| 287 | params->SlowSlewRateForSa = config->SlowSlewRateForSa; |
| 288 | params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa; |
| 289 | params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt; |
| 290 | params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; |
| 291 | |
Rizwan Qureshi | ffe5810 | 2017-02-10 15:58:24 +0530 | [diff] [blame] | 292 | /* Enable PMC XRAM read */ |
| 293 | tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; |
| 294 | |
Subrata Banik | 6b45ee4 | 2017-05-12 11:43:57 +0530 | [diff] [blame] | 295 | /* Enable/Disable EIST */ |
| 296 | tconfig->Eist = config->eist_enable; |
| 297 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 298 | soc_irq_settings(params); |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 299 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 300 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 301 | struct pci_operations soc_pci_ops = { |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 302 | .set_subsystem = &pci_dev_set_subsystem |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 303 | }; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 304 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 305 | /* Mainboard GPIO Configuration */ |
| 306 | __attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 307 | { |
| 308 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 309 | } |