blob: 93bfb1fccd8fa473c9ce0c1fdfb9a8cb0307cb81 [file] [log] [blame]
Raul E Rangel0b123dd2021-02-12 15:13:57 -07001/* SPDX-License-Identifier: GPL-2.0-only */
2
3Device(PCI0) {
4 Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
5 Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Elyes Haouas0ff941d2022-02-16 16:48:48 +01006 External(TOM1, IntObj) /* Generated by root_complex.c */
Raul E Rangel0b123dd2021-02-12 15:13:57 -07007
8 Method(_BBN, 0, NotSerialized) {
Felix Singer9df60d32022-12-26 09:43:07 +01009 Return(0) /* Bus number = 0 */
Raul E Rangel0b123dd2021-02-12 15:13:57 -070010 }
11
12 Method(_STA, 0, NotSerialized) {
13 Return(0x0B) /* Status is visible */
14 }
15
16 /* Operating System Capabilities Method */
17 Method(_OSC, 4) {
18 CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */
19
20 /* Check for proper PCI/PCIe UUID */
21 If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) {
22 /* Let OS control everything */
23 Return (Arg3)
24 } Else {
25 CDW1 |= 4 /* Unrecognized UUID */
26 Return (Arg3)
27 }
28 }
29 Name(CRES, ResourceTemplate() {
30 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
31 0x0000, /* address granularity */
32 0x0000, /* range minimum */
33 0x00ff, /* range maximum */
34 0x0000, /* translation */
35 0x0100, /* length */
36 ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
37
38 IO(Decode16, 0x0cf8, 0x0cf8, 1, 8)
39
40 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
41 0x0000, /* address granularity */
42 0x0000, /* range minimum */
43 0x0cf7, /* range maximum */
44 0x0000, /* translation */
45 0x0cf8 /* length */
46 )
47
48 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
49 0x0000, /* address granularity */
50 0x0d00, /* range minimum */
51 0xffff, /* range maximum */
52 0x0000, /* translation */
53 0xf300 /* length */
54 )
55
56 Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */
57 Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
58
59 /* memory space for PCI BARs below 4GB */
60 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
61 })
62
63 Method(_CRS, 0) {
64 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
65 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
66
67 /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
68 MM1B = TOM1
Shelley Chen4e9bb332021-10-20 15:43:45 -070069 Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
Raul E Rangel0b123dd2021-02-12 15:13:57 -070070 Local0 -= TOM1
71 MM1L = Local0
72
73 CreateWordField(CRES, ^PSB0._MAX, BMAX)
74 CreateWordField(CRES, ^PSB0._LEN, BLEN)
Shelley Chen4e9bb332021-10-20 15:43:45 -070075 BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
76 BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
Raul E Rangel0b123dd2021-02-12 15:13:57 -070077
78 Return(CRES) /* note to change the Name buffer */
79 } /* end of Method(_SB.PCI0._CRS) */
80
Raul E Rangel7e965182021-02-19 08:59:01 -070081 /* 0:14.3 - LPC */
82 #include <soc/amd/common/acpi/lpc.asl>
83
Raul E Rangel0b123dd2021-02-12 15:13:57 -070084} /* End PCI0 scope */