Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 2 | |
| 3 | #include <soc/gpe.h> |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 4 | |
Edward O'Callaghan | 8112841 | 2020-06-24 09:45:49 +1000 | [diff] [blame] | 5 | #define PORTSCN_OFFSET 0x480 |
| 6 | #define PORTSCXUSB3_OFFSET 0x540 |
| 7 | |
| 8 | #define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000 |
| 9 | #define RO_BITS_OFF_MASK ~0x80FE0012 |
| 10 | |
| 11 | /* |
| 12 | * USB Port Wake Enable (UPWE) on usb attach/detach |
| 13 | * Arg0 - Port Number |
| 14 | * Arg1 - Port 1 Status and control offset |
| 15 | * Arg2 - xHCI Memory-mapped address |
| 16 | */ |
| 17 | Method (UPWE, 3, Serialized) |
| 18 | { |
| 19 | Local0 = Arg1 + ((Arg0 - 1) * 0x10) |
| 20 | |
| 21 | /* Map ((XMEM << 16) + Local0 in PSCR */ |
Felix Singer | 372573e | 2022-12-16 03:49:55 +0100 | [diff] [blame] | 22 | OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) |
Edward O'Callaghan | 8112841 | 2020-06-24 09:45:49 +1000 | [diff] [blame] | 23 | Field (PSCR, DWordAcc, NoLock, Preserve) |
| 24 | { |
| 25 | PSCT, 32, |
| 26 | } |
| 27 | Local0 = PSCT |
| 28 | /* |
| 29 | * And port status/control reg with RO and RWS bits |
| 30 | * RO bits: 0, 2:3, 10:13, 24, 28:30 |
| 31 | * RWS bits: 5:9, 14:16, 25:27 |
| 32 | */ |
| 33 | Local0 = Local0 & RO_BITS_OFF_MASK |
| 34 | /* Set WCE and WDE bits */ |
| 35 | Local0 = Local0 | WAKE_ON_CONNECT_DISCONNECT_ENABLE |
| 36 | PSCT = Local0 |
| 37 | } |
| 38 | |
| 39 | /* |
| 40 | * USB Wake Enable Setup (UWES) |
| 41 | * Arg0 - Port enable bitmap |
| 42 | * Arg1 - Port 1 Status and control offset |
| 43 | * Arg2 - xHCI Memory-mapped address |
| 44 | */ |
| 45 | Method (UWES, 3, Serialized) |
| 46 | { |
| 47 | Local0 = Arg0 |
| 48 | |
Felix Singer | 7b8ac00 | 2022-12-26 08:45:56 +0100 | [diff] [blame] | 49 | While (1) { |
Edward O'Callaghan | 8112841 | 2020-06-24 09:45:49 +1000 | [diff] [blame] | 50 | FindSetRightBit (Local0, Local1) |
| 51 | If (Local1 == Zero) { |
| 52 | Break |
| 53 | } |
| 54 | UPWE (Local1, Arg1, Arg2) |
| 55 | /* |
| 56 | * Clear the lowest set bit in Local0 since it was |
| 57 | * processed. |
| 58 | */ |
| 59 | Local0 = Local0 & (Local0 - 1) |
| 60 | } |
| 61 | } |
| 62 | |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 63 | /* XHCI Controller 0:14.0 */ |
| 64 | |
| 65 | Device (XHCI) |
| 66 | { |
| 67 | Name (_ADR, 0x00140000) |
| 68 | |
Patrick Rudolph | 7c8de86 | 2021-01-07 16:47:23 +0100 | [diff] [blame] | 69 | Name (_PRW, Package () { GPE0_PME_B0, 4 }) |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 70 | |
Edward O'Callaghan | 8112841 | 2020-06-24 09:45:49 +1000 | [diff] [blame] | 71 | Method (_DSW, 3) |
| 72 | { |
| 73 | UWES ((\U2WE & 0xFFF), PORTSCN_OFFSET, XMEM) |
| 74 | UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM) |
| 75 | } |
| 76 | |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 77 | Name (_S3D, 3) /* D3 supported in S3 */ |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 78 | Name (_S0W, 3) /* D3 can wake device in S0 */ |
| 79 | Name (_S3W, 3) /* D3 can wake system from S3 */ |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 80 | |
Patrick Rudolph | 7c8de86 | 2021-01-07 16:47:23 +0100 | [diff] [blame] | 81 | Name (_S4D, 3) /* D3 supported in S4 */ |
| 82 | Name (_S4W, 3) /* D3 can wake system from S4 */ |
| 83 | |
Edward O'Callaghan | 8112841 | 2020-06-24 09:45:49 +1000 | [diff] [blame] | 84 | OperationRegion (XPRT, PCI_Config, 0x00, 0x100) |
| 85 | Field (XPRT, AnyAcc, NoLock, Preserve) |
| 86 | { |
| 87 | Offset (0x10), |
| 88 | , 16, |
| 89 | XMEM, 16, /* MEM_BASE */ |
| 90 | } |
| 91 | |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 92 | Method (_PS0, 0, Serialized) |
| 93 | { |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 94 | |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | Method (_PS3, 0, Serialized) |
| 98 | { |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 99 | |
Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | /* Root Hub for Cannonlake-LP PCH */ |
| 103 | Device (RHUB) |
| 104 | { |
| 105 | Name (_ADR, Zero) |
| 106 | |
| 107 | /* USB2 */ |
| 108 | Device (HS01) { Name (_ADR, 1) } |
| 109 | Device (HS02) { Name (_ADR, 2) } |
| 110 | Device (HS03) { Name (_ADR, 3) } |
| 111 | Device (HS04) { Name (_ADR, 4) } |
| 112 | Device (HS05) { Name (_ADR, 5) } |
| 113 | Device (HS06) { Name (_ADR, 6) } |
| 114 | Device (HS07) { Name (_ADR, 7) } |
| 115 | Device (HS08) { Name (_ADR, 8) } |
| 116 | Device (HS09) { Name (_ADR, 9) } |
| 117 | Device (HS10) { Name (_ADR, 10) } |
| 118 | Device (HS11) { Name (_ADR, 11) } |
| 119 | Device (HS12) { Name (_ADR, 12) } |
| 120 | |
| 121 | /* USBr */ |
| 122 | Device (USR1) { Name (_ADR, 11) } |
| 123 | Device (USR2) { Name (_ADR, 12) } |
| 124 | |
| 125 | /* USB3 */ |
| 126 | Device (SS01) { Name (_ADR, 13) } |
| 127 | Device (SS02) { Name (_ADR, 14) } |
| 128 | Device (SS03) { Name (_ADR, 15) } |
| 129 | Device (SS04) { Name (_ADR, 16) } |
| 130 | Device (SS05) { Name (_ADR, 17) } |
| 131 | Device (SS06) { Name (_ADR, 18) } |
| 132 | } |
| 133 | } |