| Angel Pons | 9c8c858 | 2022-05-06 23:22:11 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <device/mmio.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include <southbridge/intel/lynxpoint/pch.h> |
| 6 | #include <types.h> |
| 7 | |
| 8 | #define TBARB_TEMP 0x40000000 |
| 9 | |
| 10 | #define THERMAL_DEV PCI_DEV(0, 0x1f, 6) |
| 11 | |
| 12 | /* Early thermal init, it may need to be done prior to giving ME its memory */ |
| 13 | void early_thermal_init(void) |
| 14 | { |
| 15 | /* Program address for temporary BAR */ |
| 16 | pci_write_config32(THERMAL_DEV, 0x40, TBARB_TEMP); |
| 17 | pci_write_config32(THERMAL_DEV, 0x44, 0); |
| 18 | |
| 19 | /* Activate temporary BAR */ |
| 20 | pci_or_config32(THERMAL_DEV, 0x40, 1); |
| 21 | |
| 22 | /* |
| 23 | * BWG section 17.3.1 says: |
| 24 | * |
| 25 | * ### Initializing Lynx Point Thermal Sensors ### |
| 26 | * |
| 27 | * The System BIOS must perform the following steps to initialize the Lynx |
| 28 | * Point thermal subsystem device, D31:F6. The System BIOS is required to |
| 29 | * repeat this process on a resume from Sx. BIOS may enable any or all of |
| 30 | * the registers below based on OEM's platform configuration. Intel does |
| 31 | * not recommend a value on some of the registers, since each platform has |
| 32 | * different temperature trip points and one may enable a trip to cause an |
| 33 | * SMI while another platform would cause an interrupt instead. |
| 34 | * |
| 35 | * The recommended flow for enabling thermal sensor is by setting up various |
| 36 | * temperature trip points first, followed by enabling the desired trip |
| 37 | * alert method and then enable the actual sensors from TSEL registers. |
| 38 | * If this flow is not followed, software will need to take special care |
| 39 | * to handle false events during setting up those registers. |
| 40 | */ |
| 41 | |
| 42 | /* Step 1: Program CTT */ |
| 43 | write16p(TBARB_TEMP + 0x10, 0x0154); |
| 44 | |
| 45 | /* Step 2: Clear trip status from TSS and TAS */ |
| 46 | write8p(TBARB_TEMP + 0x06, 0xff); |
| 47 | write8p(TBARB_TEMP + 0x80, 0xff); |
| 48 | |
| 49 | /* Step 3: Program TSGPEN and TSPIEN to zero */ |
| 50 | write8p(TBARB_TEMP + 0x84, 0x00); |
| 51 | write8p(TBARB_TEMP + 0x82, 0x00); |
| 52 | |
| 53 | /* |
| 54 | * Step 4: If thermal reporting to an EC over SMBus is supported, |
| 55 | * then write 0x01 to TSREL, else leave at default. |
| 56 | */ |
| 57 | write8p(TBARB_TEMP + 0x0a, 0x01); |
| 58 | |
| 59 | /* Disable temporary BAR */ |
| 60 | pci_and_config32(THERMAL_DEV, 0x40, ~1); |
| 61 | |
| 62 | /* Clear temporary BAR address */ |
| 63 | pci_write_config32(THERMAL_DEV, 0x40, 0); |
| 64 | } |