Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 15 | */ |
| 16 | |
Martin Roth | ec23f04 | 2017-11-22 19:21:55 -0700 | [diff] [blame] | 17 | /* System Bus */ |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 18 | /* _SB.PCI0 */ |
| 19 | |
| 20 | /* Operating System Capabilities Method */ |
| 21 | Method(_OSC,4) |
| 22 | { |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 23 | /* Check for proper PCI/PCIe UUID */ |
| 24 | If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) |
| 25 | { |
| 26 | /* Let OS control everything */ |
| 27 | Return (Arg3) |
| 28 | } Else { |
Marc Jones | 1faa11e | 2018-08-15 22:17:45 -0600 | [diff] [blame] | 29 | CreateDWordField(Arg3,0,CDW1) |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 30 | Or(CDW1,4,CDW1) // Unrecognized UUID |
| 31 | Return(Arg3) |
| 32 | } |
| 33 | } |
| 34 | |
| 35 | /* Describe the Southbridge devices */ |
| 36 | |
| 37 | /* 0:11.0 - SATA */ |
| 38 | Device(STCR) { |
| 39 | Name(_ADR, 0x00110000) |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 40 | } /* end STCR */ |
| 41 | |
| 42 | /* 0:14.0 - SMBUS */ |
| 43 | Device(SBUS) { |
| 44 | Name(_ADR, 0x00140000) |
| 45 | } /* end SBUS */ |
| 46 | |
| 47 | #include "usb.asl" |
| 48 | |
| 49 | /* 0:14.2 - HD Audio */ |
Martin Roth | 083504b | 2017-06-24 21:30:14 -0600 | [diff] [blame] | 50 | #if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 51 | #include "audio.asl" |
Marshall Dawson | 6580408 | 2016-10-31 14:17:46 -0400 | [diff] [blame] | 52 | #endif |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 53 | |
| 54 | /* 0:14.3 - LPC */ |
| 55 | #include "lpc.asl" |
| 56 | |
| 57 | /* 0:14.7 - SD Controller */ |
| 58 | Device(SDCN) { |
| 59 | Name(_ADR, 0x00140007) |
| 60 | } /* end SDCN */ |
| 61 | |
| 62 | Name(CRES, ResourceTemplate() { |
| 63 | /* Set the Bus number and Secondary Bus number for the PCI0 device |
| 64 | * The Secondary bus range for PCI0 lets the system |
| 65 | * know what bus values are allowed on the downstream |
| 66 | * side of this PCI bus if there is a PCI-PCI bridge. |
| 67 | * PCI busses can have 256 secondary busses which |
| 68 | * range from [0-0xFF] but they do not need to be |
| 69 | * sequential. |
| 70 | */ |
| 71 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 72 | 0x0000, /* address granularity */ |
| 73 | 0x0000, /* range minimum */ |
| 74 | 0x00FF, /* range maximum */ |
| 75 | 0x0000, /* translation */ |
| 76 | 0x0100, /* length */ |
| 77 | ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ |
| 78 | |
| 79 | IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) |
| 80 | |
| 81 | WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 82 | 0x0000, /* address granularity */ |
| 83 | 0x0000, /* range minimum */ |
| 84 | 0x0CF7, /* range maximum */ |
| 85 | 0x0000, /* translation */ |
| 86 | 0x0CF8 /* length */ |
| 87 | ) |
| 88 | WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 89 | 0x0000, /* address granularity */ |
| 90 | 0x03B0, /* range minimum */ |
| 91 | 0x03DF, /* range maximum */ |
| 92 | 0x0000, /* translation */ |
| 93 | 0x0030 /* length */ |
| 94 | ) |
| 95 | |
| 96 | WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 97 | 0x0000, /* address granularity */ |
| 98 | 0x0D00, /* range minimum */ |
| 99 | 0xFFFF, /* range maximum */ |
| 100 | 0x0000, /* translation */ |
| 101 | 0xF300 /* length */ |
| 102 | ) |
| 103 | |
| 104 | Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ |
| 105 | Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ |
| 106 | |
| 107 | /* memory space for PCI BARs below 4GB */ |
| 108 | Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) |
| 109 | }) /* End Name(_SB.PCI0.CRES) */ |
| 110 | |
| 111 | Method(_CRS, 0) { |
| 112 | /* DBGO("\\_SB\\PCI0\\_CRS\n") */ |
| 113 | CreateDWordField(CRES, ^MMIO._BAS, MM1B) |
| 114 | CreateDWordField(CRES, ^MMIO._LEN, MM1L) |
| 115 | |
| 116 | /* |
| 117 | * Declare memory between TOM1 and 4GB as available |
| 118 | * for PCI MMIO. |
| 119 | * Use ShiftLeft to avoid 64bit constant (for XP). |
| 120 | * This will work even if the OS does 32bit arithmetic, as |
| 121 | * 32bit (0x00000000 - TOM1) will wrap and give the same |
| 122 | * result as 64bit (0x100000000 - TOM1). |
| 123 | */ |
| 124 | Store(TOM1, MM1B) |
| 125 | ShiftLeft(0x10000000, 4, Local0) |
| 126 | Subtract(Local0, TOM1, Local0) |
| 127 | Store(Local0, MM1L) |
| 128 | |
| 129 | Return(CRES) /* note to change the Name buffer */ |
| 130 | } /* end of Method(_SB.PCI0._CRS) */ |
| 131 | |
Elyes HAOUAS | 9985060 | 2019-02-21 16:38:43 +0100 | [diff] [blame^] | 132 | #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) |
| 133 | /* TODO: It is unstable. |
| 134 | * might be fixed by restructuring |
| 135 | */ |
| 136 | #include "acpi/AmdImc.asl" /* Hudson IMC function */ |
| 137 | #endif |
| 138 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 139 | /* |
| 140 | * |
| 141 | * FIRST METHOD CALLED UPON BOOT |
| 142 | * |
| 143 | * 1. If debugging, print current OS and ACPI interpreter. |
| 144 | * 2. Get PCI Interrupt routing from ACPI VSM, this |
| 145 | * value is based on user choice in BIOS setup. |
| 146 | */ |
| 147 | Method(_INI, 0) { |
| 148 | /* DBGO("\\_SB\\_INI\n") */ |
| 149 | /* DBGO(" DSDT.ASL code from ") */ |
| 150 | /* DBGO(__DATE__) */ |
| 151 | /* DBGO(" ") */ |
| 152 | /* DBGO(__TIME__) */ |
| 153 | /* DBGO("\n Sleep states supported: ") */ |
| 154 | /* DBGO("\n") */ |
| 155 | /* DBGO(" \\_OS=") */ |
| 156 | /* DBGO(\_OS) */ |
| 157 | /* DBGO("\n \\_REV=") */ |
| 158 | /* DBGO(\_REV) */ |
| 159 | /* DBGO("\n") */ |
| 160 | |
| 161 | /* Determine the OS we're running on */ |
| 162 | OSFL() |
| 163 | |
Kyösti Mälkki | f40f209 | 2017-01-28 09:48:29 +0200 | [diff] [blame] | 164 | #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) |
Kyösti Mälkki | f40f209 | 2017-01-28 09:48:29 +0200 | [diff] [blame] | 165 | #if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) |
WANG Siyuan | c7667f0 | 2015-06-23 22:28:17 +0800 | [diff] [blame] | 166 | ITZE() /* enable IMC Fan Control*/ |
| 167 | #endif |
Kyösti Mälkki | f40f209 | 2017-01-28 09:48:29 +0200 | [diff] [blame] | 168 | #endif |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 169 | } /* End Method(_SB._INI) */ |
| 170 | |
| 171 | Method(OSFL, 0){ |
| 172 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 173 | if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 174 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 175 | if (CondRefOf(\_OSI)) |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 176 | { |
| 177 | Store(1, OSVR) /* Assume some form of XP */ |
| 178 | if (\_OSI("Windows 2006")) /* Vista */ |
| 179 | { |
| 180 | Store(2, OSVR) |
| 181 | } |
| 182 | } else { |
| 183 | If(WCMP(\_OS,"Linux")) { |
| 184 | Store(3, OSVR) /* Linux */ |
| 185 | } Else { |
| 186 | Store(4, OSVR) /* Gotta be WinCE */ |
| 187 | } |
| 188 | } |
| 189 | Return(OSVR) |
| 190 | } |