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Kyösti Mälkkie8b4da22014-10-21 18:22:32 +03001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030015 */
16
17/* South Bridge */
18/* _SB.PCI0 */
19
20/* Operating System Capabilities Method */
21Method(_OSC,4)
22{
23 // Create DWord-addressable fields from the Capabilities Buffer
24 CreateDWordField(Arg3,0,CDW1)
25 CreateDWordField(Arg3,4,CDW2)
26 CreateDWordField(Arg3,8,CDW3)
27
28 /* Check for proper PCI/PCIe UUID */
29 If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
30 {
31 /* Let OS control everything */
32 Return (Arg3)
33 } Else {
34 Or(CDW1,4,CDW1) // Unrecognized UUID
35 Return(Arg3)
36 }
37}
38
39/* Describe the Southbridge devices */
40
41/* 0:11.0 - SATA */
42Device(STCR) {
43 Name(_ADR, 0x00110000)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030044} /* end STCR */
45
46/* 0:14.0 - SMBUS */
47Device(SBUS) {
48 Name(_ADR, 0x00140000)
49} /* end SBUS */
50
51#include "usb.asl"
52
53/* 0:14.2 - HD Audio */
Marshall Dawson65804082016-10-31 14:17:46 -040054#if !CONFIG_SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030055#include "audio.asl"
Marshall Dawson65804082016-10-31 14:17:46 -040056#endif
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030057
58/* 0:14.3 - LPC */
59#include "lpc.asl"
60
61/* 0:14.7 - SD Controller */
62Device(SDCN) {
63 Name(_ADR, 0x00140007)
64} /* end SDCN */
65
66Name(CRES, ResourceTemplate() {
67 /* Set the Bus number and Secondary Bus number for the PCI0 device
68 * The Secondary bus range for PCI0 lets the system
69 * know what bus values are allowed on the downstream
70 * side of this PCI bus if there is a PCI-PCI bridge.
71 * PCI busses can have 256 secondary busses which
72 * range from [0-0xFF] but they do not need to be
73 * sequential.
74 */
75 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
76 0x0000, /* address granularity */
77 0x0000, /* range minimum */
78 0x00FF, /* range maximum */
79 0x0000, /* translation */
80 0x0100, /* length */
81 ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
82
83 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
84
85 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
86 0x0000, /* address granularity */
87 0x0000, /* range minimum */
88 0x0CF7, /* range maximum */
89 0x0000, /* translation */
90 0x0CF8 /* length */
91 )
92 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
93 0x0000, /* address granularity */
94 0x03B0, /* range minimum */
95 0x03DF, /* range maximum */
96 0x0000, /* translation */
97 0x0030 /* length */
98 )
99
100 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
101 0x0000, /* address granularity */
102 0x0D00, /* range minimum */
103 0xFFFF, /* range maximum */
104 0x0000, /* translation */
105 0xF300 /* length */
106 )
107
108 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
109 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
110
111 /* memory space for PCI BARs below 4GB */
112 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
113}) /* End Name(_SB.PCI0.CRES) */
114
115Method(_CRS, 0) {
116 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
117 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
118 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
119
120 /*
121 * Declare memory between TOM1 and 4GB as available
122 * for PCI MMIO.
123 * Use ShiftLeft to avoid 64bit constant (for XP).
124 * This will work even if the OS does 32bit arithmetic, as
125 * 32bit (0x00000000 - TOM1) will wrap and give the same
126 * result as 64bit (0x100000000 - TOM1).
127 */
128 Store(TOM1, MM1B)
129 ShiftLeft(0x10000000, 4, Local0)
130 Subtract(Local0, TOM1, Local0)
131 Store(Local0, MM1L)
132
133 Return(CRES) /* note to change the Name buffer */
134} /* end of Method(_SB.PCI0._CRS) */
135
136/*
137 *
138 * FIRST METHOD CALLED UPON BOOT
139 *
140 * 1. If debugging, print current OS and ACPI interpreter.
141 * 2. Get PCI Interrupt routing from ACPI VSM, this
142 * value is based on user choice in BIOS setup.
143 */
144Method(_INI, 0) {
145 /* DBGO("\\_SB\\_INI\n") */
146 /* DBGO(" DSDT.ASL code from ") */
147 /* DBGO(__DATE__) */
148 /* DBGO(" ") */
149 /* DBGO(__TIME__) */
150 /* DBGO("\n Sleep states supported: ") */
151 /* DBGO("\n") */
152 /* DBGO(" \\_OS=") */
153 /* DBGO(\_OS) */
154 /* DBGO("\n \\_REV=") */
155 /* DBGO(\_REV) */
156 /* DBGO("\n") */
157
158 /* Determine the OS we're running on */
159 OSFL()
160
WANG Siyuanc7667f02015-06-23 22:28:17 +0800161#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300162 /* TODO: It is unstable. */
WANG Siyuanc7667f02015-06-23 22:28:17 +0800163 #include "acpi/AmdImc.asl" /* Hudson IMC function */
164 ITZE() /* enable IMC Fan Control*/
165#endif
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300166} /* End Method(_SB._INI) */
167
168Method(OSFL, 0){
169
Elyes HAOUASba28e8d2016-08-31 19:22:16 +0200170 if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300171
Elyes HAOUASba28e8d2016-08-31 19:22:16 +0200172 if (CondRefOf(\_OSI))
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300173 {
174 Store(1, OSVR) /* Assume some form of XP */
175 if (\_OSI("Windows 2006")) /* Vista */
176 {
177 Store(2, OSVR)
178 }
179 } else {
180 If(WCMP(\_OS,"Linux")) {
181 Store(3, OSVR) /* Linux */
182 } Else {
183 Store(4, OSVR) /* Gotta be WinCE */
184 }
185 }
186 Return(OSVR)
187}