| Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2 | |
| 3 | #ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H |
| 4 | #define NORTHBRIDGE_INTEL_GM45_CHIP_H |
| 5 | |
| Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 6 | #include <drivers/intel/gma/i915.h> |
| 7 | |
| Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 8 | struct northbridge_intel_gm45_config { |
| Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 9 | u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ |
| 10 | u16 gpu_panel_power_down_delay; /* T3 time sequence */ |
| 11 | u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ |
| 12 | u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ |
| 13 | u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ |
| Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 14 | struct i915_gpu_controller_info gfx; |
| Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 15 | u16 default_pwm_freq; |
| Arthur Heymans | 12bed26 | 2016-11-24 13:23:05 +0100 | [diff] [blame] | 16 | u8 duty_cycle; |
| Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 17 | |
| 18 | /* |
| 19 | * Maximum PCI mmio size in MiB. |
| 20 | */ |
| 21 | u16 pci_mmio_size; |
| Arthur Heymans | 98c9257 | 2022-11-07 11:39:58 +0100 | [diff] [blame^] | 22 | int slfm; |
| Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 23 | }; |
| 24 | |
| 25 | #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ |