Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 2 | |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 3 | #include <device/device.h> |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 4 | #include <delay.h> |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 5 | #include <device/pci.h> |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Sumeet R Pawnikar | 309ccf7 | 2020-05-09 16:37:30 +0530 | [diff] [blame] | 7 | #include <intelblocks/power_limit.h> |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 8 | #include <intelblocks/systemagent.h> |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 9 | #include <soc/cpu.h> |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 10 | #include <soc/iomap.h> |
| 11 | #include <soc/systemagent.h> |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 12 | #include "chip.h" |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 13 | |
| 14 | /* |
| 15 | * SoC implementation |
| 16 | * |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 17 | * Add all known fixed memory ranges for Host Controller/Memory |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 18 | * controller. |
| 19 | */ |
| 20 | void soc_add_fixed_mmio_resources(struct device *dev, int *index) |
| 21 | { |
| 22 | static const struct sa_mmio_descriptor soc_fixed_resources[] = { |
Angel Pons | 9849488 | 2021-01-29 11:35:16 +0100 | [diff] [blame^] | 23 | { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH, |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 24 | "PCIEXBAR" }, |
| 25 | { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| 26 | { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, |
| 27 | { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, |
| 28 | { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, |
| 29 | { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 30 | /* |
| 31 | * PMC pci device gets hidden from PCI bus due to Silicon |
| 32 | * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with |
| 33 | * SA resources to ensure that PMCBAR falls under PCI reserved |
| 34 | * memory range. |
| 35 | * |
| 36 | * Note: Don't add any more resource with same offset 0x10 |
| 37 | * under this device space. |
| 38 | */ |
| 39 | { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, |
| 40 | "PMCBAR" }, |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 41 | }; |
| 42 | |
| 43 | sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |
| 44 | ARRAY_SIZE(soc_fixed_resources)); |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 45 | |
| 46 | /* Add Vt-d resources if VT-d is enabled. */ |
| 47 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) |
| 48 | return; |
| 49 | |
John Zhao | 1159a16 | 2019-04-22 10:45:51 -0700 | [diff] [blame] | 50 | sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 51 | ARRAY_SIZE(soc_vtd_resources)); |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | /* |
| 55 | * SoC implementation |
| 56 | * |
| 57 | * Perform System Agent Initialization during Ramstage phase. |
| 58 | */ |
| 59 | void soc_systemagent_init(struct device *dev) |
| 60 | { |
Sumeet R Pawnikar | 309ccf7 | 2020-05-09 16:37:30 +0530 | [diff] [blame] | 61 | struct soc_power_limits_config *soc_config; |
| 62 | config_t *config; |
| 63 | |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 64 | /* Enable Power Aware Interrupt Routing */ |
| 65 | enable_power_aware_intr(); |
| 66 | |
| 67 | /* Enable BIOS Reset CPL */ |
| 68 | enable_bios_reset_cpl(); |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 69 | |
| 70 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 71 | mdelay(1); |
Sumeet R Pawnikar | 309ccf7 | 2020-05-09 16:37:30 +0530 | [diff] [blame] | 72 | config = config_of_soc(); |
| 73 | soc_config = &config->power_limits_config; |
| 74 | set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 75 | } |
Patrick Rudolph | bf72dcb | 2020-05-12 16:04:47 +0200 | [diff] [blame] | 76 | |
| 77 | uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) |
| 78 | { |
| 79 | switch (capid0_a_ddrsz) { |
| 80 | case 1: |
| 81 | return 8192; |
| 82 | case 2: |
| 83 | return 4096; |
| 84 | case 3: |
| 85 | return 2048; |
| 86 | default: |
| 87 | return 32768; |
| 88 | } |
| 89 | } |