Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * Copyright (C) 2015-2017 Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 20 | #include <device/pci.h> |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 21 | #include <intelblocks/systemagent.h> |
| 22 | #include <soc/iomap.h> |
| 23 | #include <soc/systemagent.h> |
| 24 | |
| 25 | /* |
| 26 | * SoC implementation |
| 27 | * |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame^] | 28 | * Add all known fixed memory ranges for Host Controller/Memory |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 29 | * controller. |
| 30 | */ |
| 31 | void soc_add_fixed_mmio_resources(struct device *dev, int *index) |
| 32 | { |
| 33 | static const struct sa_mmio_descriptor soc_fixed_resources[] = { |
| 34 | { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, |
| 35 | "PCIEXBAR" }, |
| 36 | { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| 37 | { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, |
| 38 | { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, |
| 39 | { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, |
| 40 | { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 41 | /* |
| 42 | * PMC pci device gets hidden from PCI bus due to Silicon |
| 43 | * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with |
| 44 | * SA resources to ensure that PMCBAR falls under PCI reserved |
| 45 | * memory range. |
| 46 | * |
| 47 | * Note: Don't add any more resource with same offset 0x10 |
| 48 | * under this device space. |
| 49 | */ |
| 50 | { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, |
| 51 | "PMCBAR" }, |
Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 52 | }; |
| 53 | |
| 54 | sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |
| 55 | ARRAY_SIZE(soc_fixed_resources)); |
| 56 | } |
| 57 | |
| 58 | /* |
| 59 | * SoC implementation |
| 60 | * |
| 61 | * Perform System Agent Initialization during Ramstage phase. |
| 62 | */ |
| 63 | void soc_systemagent_init(struct device *dev) |
| 64 | { |
| 65 | /* Enable Power Aware Interrupt Routing */ |
| 66 | enable_power_aware_intr(); |
| 67 | |
| 68 | /* Enable BIOS Reset CPL */ |
| 69 | enable_bios_reset_cpl(); |
| 70 | } |